CN-224232342-U - Display panel and display device

CN224232342UCN 224232342 UCN224232342 UCN 224232342UCN-224232342-U

Abstract

The display panel comprises a display area and a non-display area, wherein the non-display area comprises a grid driving circuit and a selection circuit, the display area comprises N refreshing areas, the grid driving circuit comprises N grid driving subcircuits, the grid driving subcircuits comprise a plurality of cascaded shift register circuits, the selection circuit comprises N selection subcircuits, the selection subcircuits comprise a first power signal end, an output end and at least two selection ends, the first power signal end is electrically connected to a first power line, the output end is electrically connected to the input end of a first stage shift register circuit of the grid driving subcircuit corresponding to the selection subcircuit, the at least two selection ends are respectively electrically connected to one selection signal line, and the first power signal end is electrically connected with the output end based on the signal accessed by the at least two selection ends as an effective level. The embodiment of the disclosure can realize the narrow frame design at the same time of realizing the display panel with multiple refreshing areas.

Inventors

LIU JINGHAO
HUA GANG
DENG LIGUANG
CHEN JUNSHENG
WANG DONG

Assignees

北京京东方显示技术有限公司
京东方科技集团股份有限公司

Dates

Publication Date: 20260512
Application Date: 20250513

Claims (10)

1. A display panel is characterized by comprising a display area and a non-display area, wherein the non-display area comprises a grid driving circuit and a selection circuit, the display area comprises N refreshing areas, The gate driving circuit includes N gate driving sub-circuits, each including a plurality of shift register circuits in cascade, the shift register circuits providing scanning signals to pixel circuits of corresponding rows in a display area, the selection circuit including N selection sub-circuits, The selection sub-circuit comprises a first power signal end, an output end and at least two selection ends, wherein the first power signal end is electrically connected to a first power line, the output end is electrically connected to the input end of a first stage shift register circuit of a grid driving sub-circuit corresponding to the selection sub-circuit, the at least two selection ends are respectively electrically connected to the selection signal line and are configured to electrically connect the first power signal end with the output end based on the signal accessed by the at least two selection ends as an effective level, Wherein N is an integer greater than or equal to 2.
2. The display panel of claim 1, wherein the selection sub-circuit comprises M selection switches connected in series, a first pole of an n+1th selection switch of the M selection switches is electrically connected to a second pole of the n selection switch, a first pole of the 1 st selection switch is electrically connected to the first power signal terminal, a second pole of the M selection switch is electrically connected to an output terminal of the selection sub-circuit, control poles of the M selection switches are respectively electrically connected to the at least two selection terminals, Wherein n is an integer of 1 or more and less than M, M is an integer of 2 or more.
3. The display panel of claim 2, wherein the M selection switches are each N-type transistors or each P-type transistors.
4. The display panel of claim 2, wherein the display panel comprises, The display panel comprises K selection signal lines, wherein K satisfies the following conditions: 。
5. The display panel of claim 1, wherein the shift register circuit comprises an input sub-circuit, a pull-up sub-circuit, a pull-down control sub-circuit, and a pull-down sub-circuit, The input sub-circuit is electrically connected between an input terminal of the shift register circuit and a pull-up node, configured to transmit an active level signal to the pull-up node based on a signal of the input terminal of the shift register circuit, The pull-up sub-circuit is electrically connected to a first clock signal terminal, an output terminal of the shift register circuit, and the pull-up node, configured to electrically connect the first clock signal terminal with the output terminal based on a signal of the pull-up node, The pull-down control sub-circuit is electrically connected between a second power signal terminal and a first pull-down node, is configured to electrically connect the second power signal terminal with the first pull-down node based on a first power signal of the second power signal terminal, The pull-down subcircuit is electrically connected to the first pull-down node, a third power signal terminal, and the pull-up node, and is configured to electrically connect the third power signal terminal with the first pull-down node based on a signal of the pull-up node.
6. The display panel of claim 1, wherein the shift register circuit comprises an input sub-circuit, a first control sub-circuit, and an output sub-circuit, An input sub-circuit electrically connected to an input terminal of the shift register circuit, a first node, and a second clock signal terminal, configured to electrically connect the input terminal of the shift register circuit with the first node based on a signal of the second clock signal terminal; A first control sub-circuit electrically connected to a fourth power signal terminal, a second node, and the second clock signal terminal, configured to electrically connect the fourth power signal terminal with the second node based on a signal of the second clock signal terminal; An output sub-circuit electrically connected to a third node, a third clock signal terminal, and an output terminal, configured to output a signal of the third clock signal terminal to the output terminal of the shift register circuit based on a signal of the third node; And an output control sub-circuit electrically connected to the second node, a fifth power signal terminal, and the output terminal, and configured to electrically connect the fifth power signal terminal with the output terminal of the shift register circuit based on a signal of the second node.
7. The display panel according to claim 4 or 5, wherein, The first power supply signal end is connected with a high-level signal, and the transistor in the display panel is a metal oxide thin film transistor.
8. The display panel according to claim 7, wherein the transistors in the shift register circuit are N-type transistors, and the first power signal terminal is connected to a high level signal.
9. The display panel of claim 2, wherein the selection sub-circuit comprises two selection switches.
10. A display device comprising the display panel of any one of claims 1-9.

Description

Display panel and display device Technical Field The disclosure relates to the field of display technologies, and in particular, to a display panel and a display device. Background At present, the electronic paper screen has the characteristics of low power consumption, wide viewing angle, eye protection and the like, and the application field is wider and wider. In the scenes of billboards, commodity labels, signs and the like, a long-strip-shaped electronic paper screen is often used. However, at present, if a module mode of splicing a plurality of screens is adopted, the problem of high cost of driving chips is brought, and if a multi-refresh area is adopted, the problems of a plurality of signal lines and limited number of refresh areas are brought. Disclosure of utility model In order to solve at least one of the above problems, a first aspect of the present disclosure provides a display panel including a display region and a non-display region, the non-display region including a gate driving circuit and a selection circuit, the display region including N refresh regions, The gate driving circuit includes N gate driving sub-circuits, each including a plurality of shift register circuits in cascade, the shift register circuits providing scanning signals to the pixel circuits of the corresponding row in the display area, the selection circuit includes N selection sub-circuits, The selection sub-circuit comprises a first power supply signal end, an output end and at least two selection ends, wherein the first power supply signal end is electrically connected to a first power supply line, the output end is electrically connected to the input end of a first stage shift register circuit of a grid driving sub-circuit corresponding to the selection sub-circuit, the at least two selection ends are respectively electrically connected to one selection signal line, the first power supply signal end and the output end are electrically connected based on signals accessed by the at least two selection ends as effective levels, Wherein N is an integer greater than or equal to 2. Optionally, the selection sub-circuit comprises M selection switches connected in series, a first pole of an n+1th selection switch in the M selection switches is electrically connected to a second pole of the n selection switch, a first pole of the 1 st selection switch is electrically connected to the first power supply signal terminal, a second pole of the M selection switch is electrically connected to an output terminal of the selection sub-circuit, control poles of the M selection switches are respectively electrically connected to at least two selection terminals, Wherein n is an integer of 1 or more and less than M, M is an integer of 2 or more. Optionally, at least two of the selection switches are both N-type transistors or both P-type transistors. Optionally, the display panel further includes K selection signal lines, K satisfying: Optionally, the shift register circuit includes an input sub-circuit, a pull-up sub-circuit, a pull-down control sub-circuit and a pull-down sub-circuit, The input sub-circuit is electrically connected between the input terminal of the shift register circuit and the pull-up node, and is configured to transmit an active level signal to the pull-up node based on a signal of the input terminal of the shift register circuit, The pull-up sub-circuit is electrically connected to the first clock signal terminal, the output terminal of the shift register circuit, and the pull-up node, configured to electrically connect the first clock signal terminal with the output terminal based on a signal of the pull-up node, The pull-down control sub-circuit is electrically connected between the second power signal terminal and the first pull-down node and is configured to electrically connect the second power signal terminal with the first pull-down node based on the first power signal of the second power signal terminal, The pull-down sub-circuit is electrically connected to the first pull-down node, the third power signal terminal, and the pull-up node, and is configured to electrically connect the third power signal terminal with the first pull-down node based on a signal of the pull-up node. Optionally, the shift register circuit comprises an input sub-circuit, a first control sub-circuit and an output sub-circuit, An input sub-circuit electrically connected to an input terminal of the shift register circuit, a first node, and a second clock signal terminal, configured to electrically connect the input terminal of the shift register circuit with the first node based on a signal of the second clock signal terminal; A first control sub-circuit electrically connected to a fourth power signal terminal, a second node, and the second clock signal terminal, configured to electrically connect the fourth power signal terminal with the second node based on a signal of the second clock signal terminal; An output sub-circuit elect