CN-224232358-U - Memory body

Abstract

A memory includes a logic circuit having a first input, a second input, and an output, and a memory circuit including a transistor coupled to the logic circuit, the transistor having a semiconductor layer including a source and a drain, and a storage node having a first connection, a second connection, and a third connection. The source or the drain of the transistor is coupled to the first connection of the storage node, the logic circuit includes one or more transistors in an active region of a substrate, the one or more transistors are front end of line (FEOL) devices, and the semiconductor layer and the storage node are located in a back end of line (BEOL) layer above the substrate.

Inventors

• SHI YIJUN
• WANG YI

Assignees

• 台湾积体电路制造股份有限公司

Dates

Publication Date

20260512

Application Date

20250506

Priority Date

20240603

Claims (10)

1. 1. A kind of memory device, in which the memory device, characterized by comprising the following steps: a logic circuit having a first input, a second input and an output, and A memory circuit includes: A transistor coupled to the logic circuit, the transistor having a semiconductor layer including a source and a drain, and A storage node having a first connector, a second connector and a third connector, wherein: The source or the drain of the transistor is coupled to the first connection of the storage node, The logic circuit comprises one or more transistors in an active region of a substrate, the one or more transistors being a plurality of front-end-of-line devices, and The semiconductor layer and the storage node are located in a plurality of back-end-of-line layers above the substrate.
2. 2. The memory of claim 1, wherein: The memory circuit further includes a capacitor in the plurality of back-end-of-line layers, The third connection of the storage node is coupled to a first terminal of the capacitor, and A second terminal of the capacitor is coupled to a reference voltage.
3. 3. The memory of claim 1, wherein: the plurality of back-end-of-line layers comprises a plurality of metal layers, an At least one metal layer of the plurality of metal layers is located at a level between the semiconductor layer and the substrate.
4. 4. The memory of claim 1, wherein: The memory circuit includes the transistor, the storage node and a capacitor, The plurality of back-end-of-line layers comprises a plurality of metal layers, an At least one of the plurality of metal layers is located at a level between the capacitor and the substrate.
5. 5. The memory of claim 1, wherein: the memory includes a plurality of memory circuits, each of the plurality of memory circuits having a transistor, a capacitor and a storage node in the plurality of back-end-of-line layers, an The memory includes a plurality of logic circuits corresponding to the plurality of memory circuits, each of the plurality of logic circuits having one or more transistors in the active region.
6. 6. The memory of claim 1, wherein: the memory circuit is a first memory circuit, The memory further includes a second memory circuit having a transistor, a capacitor and a storage node in the plurality of back-end-of-line layers, The logic circuit further comprises a third input, The first input of the logic circuit is coupled to the storage node of the first memory circuit, and The third input of the logic circuit is coupled to the storage node of the second memory circuit.
7. 7. A kind of memory device, in which the memory device, characterized by comprising the following steps: a logic circuit having a first input, a second input and an output, and A memory circuit includes a storage capacitor and a transistor, Wherein: The transistor and the logic circuit are located on a first substrate, and the storage capacitor is located on a second substrate, The storage capacitor has a first terminal and a second terminal, The transistor has a source and a drain, and the source or the drain is coupled to the first terminal of the storage capacitor via a conductor including an interconnect connecting the first substrate and the second substrate, an The first input of the logic circuit is coupled to the first terminal of the storage capacitor.
8. 8. The memory of claim 7, wherein: The memory comprises a plurality of memory circuits, wherein transistors of the memory circuits are located on the first substrate and storage capacitors of the memory circuits are located on the second substrate, and Each storage capacitor of the plurality of memory circuits is coupled to a corresponding transistor through a corresponding interconnect connecting the first substrate and the second substrate.
9. 9. The memory of claim 8, wherein each storage capacitor of the plurality of memory circuits has a first terminal coupled to a corresponding logic circuit on the first substrate, The memory further includes an adder tree, the plurality of outputs of the plurality of logic circuits being coupled to the plurality of inputs of the adder tree.
10. 10. A kind of memory device, in which the memory device, characterized by comprising the following steps: a logic circuit having a first input, a second input, and an output; A substrate having an active region, the active region comprising: one or more first transistors, the one or more first transistors being a front-end-of-line device; A second transistor having a semiconductor layer including a source and a drain; a storage node electrically connected to the one of the source electrode or the drain electrode, and A capacitor having a terminal electrically connected to the other of the source or the drain, The semiconductor layer and the storage node are located in a plurality of back-end-of-line layers above the substrate.

Description

Memory body Technical Field The present disclosure relates to a memory, and more particularly, to a memory having stacked substrates. Background Recent advances in the field of artificial intelligence have resulted in a variety of products and/or applications including, for example, speech recognition, image processing, machine learning, natural language processing, and the like. These products and/or applications often move large amounts of data to and from a data processor for learning, training, cognitive operations, and the like. Disclosure of utility model One embodiment of the present disclosure includes a memory comprising a logic circuit having a first input, a second input, and an output, and a memory circuit comprising a transistor coupled to the logic circuit, the transistor having a semiconductor layer comprising a source and a drain, and a storage node having a first connection, a second connection, and a third connection, wherein the source or the drain of the transistor is coupled to the first connection of the storage node, the logic circuit comprising a transistor in an active region of a substrate, the transistor being a front end of line (FEOL) device, and the semiconductor layer and the storage node being located in a back end of line (BEOL) layer above the substrate. One embodiment of the present disclosure includes a memory comprising a logic circuit having a first input, a second input, and an output, and a memory circuit comprising a storage capacitor and a transistor, wherein the transistor and the logic circuit are located on a first substrate and the storage capacitor is located on a second substrate, the storage capacitor has a first terminal and a second terminal, the transistor has a source and a drain, and the source or drain is coupled to the first terminal of the storage capacitor by a conductor comprising an interconnect connecting the first substrate and the second substrate, and the first input of the logic circuit is coupled to the first terminal of the storage capacitor. One embodiment of the present disclosure includes a memory comprising a logic circuit having a first input, a second input, and an output, a substrate having an active region comprising one or more first transistors, the one or more first transistors being front-end-of-line devices, a second transistor having a semiconductor layer comprising a source and a drain, a storage node electrically connected to one of the source or the drain, and a capacitor having a terminal electrically connected to the other of the source or the drain, wherein the semiconductor layer and the storage node are located in a back-end-of-line layer above the substrate. Drawings The various aspects of the disclosure are best understood from the following detailed description when read with the accompanying drawing figures. It should be noted that the various features are not drawn to scale in accordance with industry standard practices. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. FIG. 1 is a block diagram of a memory according to one embodiment; FIG. 2 is a schematic diagram of a memory according to an embodiment; FIG. 3 is a schematic diagram of a neural network, according to an embodiment; FIG. 4 is a schematic diagram of an integrated circuit (INTEGRATED CIRCUIT; IC) device according to one embodiment; FIG. 5A is a circuit diagram of a monolithic 3D digital CIM DRAM bit cell according to an embodiment; FIG. 5B is a cross-sectional view of a device including a monolithic 3D digital CIM DRAM bit cell according to an embodiment; FIG. 5C is a flowchart of a method of fabricating a monolithic 3D digital CIM DRAM bit cell according to one embodiment; FIG. 6A is a circuit diagram of a heterogeneous 3D digital CIM DRAM bit cell according to one embodiment; FIG. 6B is a cross-sectional view of a device including heterogeneous 3D digital CIM DRAM bit cells according to one embodiment; FIG. 6C is a flowchart of a method of fabricating a monolithic 3D digital CIM DRAM bit cell according to one embodiment; FIG. 6D is a circuit diagram of a heterogeneous 3D digital CIM DRAM bit cell according to one embodiment; FIG. 6E is a circuit diagram of a heterogeneous 3D digital CIM DRAM bit cell according to one embodiment; FIG. 7 is a circuit diagram of a heterogeneous 3D digital CIM DRAM bit cell according to one embodiment; FIG. 8A is a circuit diagram of a heterogeneous 3D digital CIM DRAM bit cell according to one embodiment; FIG. 8B is a flowchart of a method of fabricating monolithic 3D digital CIM DRAM bit cells using active and passive substrates according to one embodiment; FIG. 9 is a diagram of a memory macro according to one embodiment; FIG. 10 is a flow chart of a method of operating a circuit according to an embodiment. [ Symbolic description ] 100 Memory 105 First memory segment 107 Second memory segment 110 Memory macro 112 Memory array 113 Memory cell 114 Weight