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CN-224233358-U - Interlocking circuit and battery management system

CN224233358UCN 224233358 UCN224233358 UCN 224233358UCN-224233358-U

Abstract

The application provides an interlocking circuit and a battery management system, wherein the interlocking circuit comprises a first power end, a first interlocking end and a voltage stabilizing sub-circuit, wherein the first power end is used for being connected with a power supply, the first interlocking end is connected with the first power end and is used for being connected with a first end of a high-voltage connector, the second interlocking end is used for being connected with a second end of the high-voltage connector, the first connecting end of the voltage stabilizing sub-circuit is connected between the first power end and the first interlocking end, the second connecting end of the voltage stabilizing sub-circuit is connected to a grounding point, and the voltage stabilizing end of the voltage stabilizing sub-circuit is connected to the second interlocking end and is used for providing a fixed voltage value.

Inventors

  • GUO LIAN

Assignees

  • 欣旺达动力科技股份有限公司

Dates

Publication Date
20260512
Application Date
20250506

Claims (10)

  1. 1. An interlock circuit, the interlock circuit comprising: A first power supply terminal (V1) for connecting to a power supply; A first interlocking terminal (K1) connected to the first power terminal (V1) and adapted to be connected to a first end of a high voltage connector (S1), -A second interlocking end (K2) for connection to a second end of the high voltage connector (S1); The voltage stabilizing sub-circuit (101), a first connecting end of the voltage stabilizing sub-circuit (101) is connected between the first power end (V1) and the first interlocking end (K1), a second connecting end of the voltage stabilizing sub-circuit (101) is connected to a ground point (GND), and a voltage stabilizing end of the voltage stabilizing sub-circuit (101) is connected to the second interlocking end (K2) for providing a fixed voltage value.
  2. 2. The interlock circuit according to claim 1, wherein the voltage regulator sub-circuit (101) comprises a voltage regulator (U1), a first resistor (R1) and a second resistor (R2), The cathode of the voltage stabilizer (U1) is used as a first connection end of the voltage stabilizer sub-circuit (101), the anode of the voltage stabilizer (U1) is used as a second connection end of the voltage stabilizer sub-circuit (101), the reference electrode of the voltage stabilizer (U1) is connected to the first end of the first resistor (R1), the second end of the first resistor (R1) is used as the voltage stabilizing end of the voltage stabilizer sub-circuit (101), the first end of the second resistor (R2) is connected to the reference electrode of the voltage stabilizer (U1), and the second end of the second resistor (R2) is connected to the ground point (GND).
  3. 3. The interlock circuit of claim 1 wherein the interlock circuit further comprises: A first interlock acquisition sub-circuit (102), a first end of the first interlock acquisition sub-circuit (102) being connected between a first connection end of the voltage stabilizing sub-circuit (101) and the first interlock end (K1), a second end of the first interlock acquisition sub-circuit (102) being a first acquisition end (Y1) for connection to a microprocessor unit; And/or a second interlocking acquisition sub-circuit (103), a first end of the second interlocking acquisition sub-circuit (103) being connected between a voltage stabilizing end of the voltage stabilizing sub-circuit (101) and the second interlocking end (K2), a second end of the second interlocking acquisition sub-circuit (103) being a second acquisition end (Y2) for connection to the micro-processing unit.
  4. 4. The interlock circuit of claim 3 wherein said first interlock acquisition sub-circuit (102) comprises a third resistor (R3) and a fourth resistor (R4), Wherein a first end of the third resistor (R3) is used as a first end of the first interlocking acquisition sub-circuit (102), a second end of the third resistor (R3) is connected to a first end of the fourth resistor (R4), a second end of the fourth resistor (R4) is connected to a ground point (GND), and a space between the third resistor (R3) and the fourth resistor (R4) is used as the first acquisition end (Y1); And/or, the second interlocking acquisition sub-circuit (103) comprises a fifth resistor (R5) and a sixth resistor (R6), Wherein a first end of the fifth resistor (R5) is used as a first end of the second interlocking acquisition sub-circuit (103), a second end of the fifth resistor (R5) is connected to a first end of the sixth resistor (R6), a second end of the sixth resistor (R6) is connected to a ground point (GND), and a second acquisition end (Y2) is used between the fifth resistor (R5) and the sixth resistor (R6).
  5. 5. The interlock circuit of claim 1 wherein said interlock circuit further comprises a switch sub-circuit (104), The first connection end of the switch sub-circuit (104) is connected to the first power supply end (V1), the second connection end of the switch sub-circuit (104) is connected to the first connection end of the voltage stabilizing sub-circuit (101), and whether the first power supply end (V1) supplies power to the voltage stabilizing sub-circuit (101) is changed by changing the on-off state of the switch sub-circuit (104).
  6. 6. The interlock circuit of claim 5 wherein said switch sub-circuit (104) comprises a current limiting unit (1041) and an isolation unit (1042), The first connection end of the current limiting unit (1041) is used as the first connection end of the switch sub-circuit (104), the second connection end of the current limiting unit (1041) is used as the second connection end of the switch sub-circuit (104), the control end of the current limiting unit (1041) is connected to the first connection end of the isolation unit (1042), the second connection end of the isolation unit (1042) is connected to the ground point (GND), and the control end of the isolation unit (1042) is used as the control end (Y3) of the switch sub-circuit (104) and is used for being connected to the micro-processing unit.
  7. 7. The interlock circuit according to claim 6, wherein the current limiting unit (1041) includes a seventh resistor (R7), an eighth resistor (R8), a ninth resistor (R9) and a first control switch (Q1), Wherein a first end of the seventh resistor (R7) is used as a first connection end of the current limiting unit (1041), a second end of the seventh resistor (R7) is connected to a first connection end of the first control switch (Q1), a second connection end of the first control switch (Q1) is used as a second connection end of the current limiting unit (1041), a control end of the first control switch (Q1) is connected to a first end of the eighth resistor (R8), a second end of the eighth resistor (R8) is connected to a second end of the seventh resistor (R7), a first end of the ninth resistor (R9) is connected to a control end of the first control switch (Q1), and a second end of the ninth resistor (R9) is used as a control end of the current limiting unit (1041); And/or, the isolation unit (1042) comprises a tenth resistor (R10), an eleventh resistor (R11) and a second control switch (Q2), The first connection end of the second control switch (Q2) is used as the first connection end of the isolation unit (1042), the second connection end of the second control switch (Q2) is used as the second connection end of the isolation unit (1042), the control end of the second control switch (Q2) is connected to the first end of the tenth resistor (R10), the second end of the tenth resistor (R10) is used as the control end of the isolation unit (1042), the first end of the eleventh resistor (R11) is connected to the control end of the second control switch (Q2), and the second end of the eleventh resistor (R11) is connected to the ground point (GND).
  8. 8. The interlock circuit according to claim 1 or 5, further comprising a fault detection subcircuit (105), a first terminal of the fault detection subcircuit (105) being for connection to a pull-up power supply (V2), a second terminal of the fault detection subcircuit (105) being connected between a voltage stabilizing terminal of the voltage stabilizing subcircuit (101) and the second interlock terminal (K2), Wherein the voltage value of the second interlocking terminal (K2) is limited to be different from the voltage value of the power supply when the high-voltage connector (S1) is not conducted by setting the voltage value of the pull-up power supply and the specification of electronic components in the fault detection sub-circuit (105).
  9. 9. The interlock circuit according to claim 8, wherein the fault detection subcircuit (105) includes a twelfth resistor (R12) and an anti-reflection diode (D1), Wherein the anode of the anti-reflection diode (D1) is used as the first end of the fault detection sub-circuit (105), the cathode of the anti-reflection diode (D1) is connected with the first end of the twelfth resistor (R12), and the second end of the twelfth resistor (R12) is used as the second end of the fault detection sub-circuit (105).
  10. 10. A battery management system, the battery management system comprising: The micro-processing unit is provided with a first acquisition pin for connecting the first interlocking end (K1), and a second acquisition pin for connecting the second interlocking end (K2); an interlock circuit as claimed in any one of claims 1 to 9; the power supply is an input power supply of the battery management system.

Description

Interlocking circuit and battery management system Technical Field The application relates to the technical field of high-voltage power supply, in particular to an interlocking circuit and a battery management system. Background With the rapid development of new energy automobiles, the performance of the battery serving as a core component directly influences the endurance, safety and service life of the automobile. The Battery management system (Battery MANAGEMENT SYSTEM, BMS) is responsible for monitoring and managing the Battery status, and in order to ensure efficient and safe operation of the Battery, it is necessary to detect in real time whether the high voltage connector in the Battery pack component is fault free and normally connected to the high voltage power supply circuit. The current common high-voltage interlocking detection scheme is to judge whether the high-voltage connector is normally connected to a high-voltage power supply circuit or not by detecting the voltages at two ends of the high-voltage connector. However, as the voltage signal fluctuates along with the voltage value input by the BMS, a wider voltage range can be set, and the voltage at the two ends of the high-voltage connector falls into the voltage range, the high-voltage connector is considered to be normally connected to the high-voltage power supply circuit, the error tolerance rate is larger due to the larger voltage range, and the safety of the high-voltage system is reduced. Disclosure of utility model Accordingly, an object of the present application is to provide an interlock circuit and a battery management system, which can prevent the voltage at two ends of a high voltage connector from being affected by the fluctuation of a power supply source by arranging a voltage stabilizing sub-circuit between a first power source end and an interlock end for connecting the high voltage connector, thereby solving the technical problem of inaccurate detection of the high voltage connector caused by the fluctuation of the voltage in the prior art and achieving the technical effects of improving the detection accuracy and the circuit safety. In a first aspect, an embodiment of the present application provides an interlock circuit, which includes a first power source terminal for connecting to a power source, a first interlock terminal connected to the first power source terminal and for connecting to a first terminal of a high voltage connector, a second interlock terminal for connecting to a second terminal of the high voltage connector, and a voltage regulator sub-circuit, wherein a first connection terminal of the voltage regulator sub-circuit is connected between the first power source terminal and the first interlock terminal, a second connection terminal of the voltage regulator sub-circuit is connected to a ground point, and a voltage regulator terminal of the voltage regulator sub-circuit is connected to the second interlock terminal for providing a fixed voltage value. Optionally, the voltage stabilizing sub-circuit includes a voltage stabilizer, a first resistor and a second resistor, wherein a cathode of the voltage stabilizer is used as a first connection end of the voltage stabilizing sub-circuit, an anode of the voltage stabilizer is used as a second connection end of the voltage stabilizing sub-circuit, a reference electrode of the voltage stabilizer is connected to the first end of the first resistor, a second end of the first resistor is used as a voltage stabilizing end of the voltage stabilizing sub-circuit, a first end of the second resistor is connected to the reference electrode of the voltage stabilizer, and a second end of the second resistor is connected to a ground point. Optionally, the interlocking circuit further comprises a first interlocking acquisition sub-circuit, wherein a first end of the first interlocking acquisition sub-circuit is connected between a first connection end of the voltage stabilizing sub-circuit and the first interlocking end, a second end of the first interlocking acquisition sub-circuit is used as a first acquisition end and is connected to the micro-processing unit, and/or a second interlocking acquisition sub-circuit, a first end of the second interlocking acquisition sub-circuit is connected between a voltage stabilizing end of the voltage stabilizing sub-circuit and the second interlocking end, and a second end of the second interlocking acquisition sub-circuit is used as a second acquisition end and is connected to the micro-processing unit. Optionally, the first interlock acquisition sub-circuit comprises a third resistor and a fourth resistor, wherein a first end of the third resistor is used as a first end of the first interlock acquisition sub-circuit, a second end of the third resistor is connected to a first end of the fourth resistor, a second end of the fourth resistor is connected to a ground point, the first acquisition end is used between the third resistor an