CN-224233652-U - Operational amplifier and chip

Abstract

The utility model discloses an operational amplifier and a chip, wherein the operational amplifier comprises an output stage, the output stage comprises a first transistor, a second transistor, a biasing unit, a first current unit, a second current unit and a control unit, the first current unit is connected with a control end of the first transistor to form a first node, the control unit is connected with a control end of the second transistor to form a second node, the biasing unit is connected with the first node and the second node, the first end of the first transistor is connected with the first end of the second transistor to form an output end of the operational amplifier, and the second current unit is connected with the second node to inject current into the second node. According to the operational amplifier and the chip, when the output voltage rises and the first current unit cannot be duplicated correctly to generate current, the second current unit can still be guaranteed to be duplicated correctly to generate current, so that the control unit can work normally, and the whole operational amplifier can work normally.

Inventors

• LEI PENG
• ZHOU QI

Assignees

• 思瑞浦微电子科技（苏州）股份有限公司

Dates

Publication Date

20260512

Application Date

20250417

Claims (10)

1. 1. The operational amplifier is characterized by comprising an output stage, wherein the output stage comprises a first transistor, a second transistor, a biasing unit, a first current unit, a second current unit and a control unit, the first current unit is connected with a control end of the first transistor to form a first node, the control unit is connected with a control end of the second transistor to form a second node, the biasing unit is connected with the first node and the second node, a second end of the first transistor is connected with a power supply voltage, a second end of the second transistor is connected with a ground voltage, a first end of the first transistor is connected with a first end of the second transistor to form an output end of the operational amplifier, and the second current unit is connected with the second node.
2. 2. The operational amplifier of claim 1, wherein the first current cell comprises a first current mirror and a first current source, the first current mirror being coupled to the first current source and to a control terminal of the first transistor.
3. 3. The operational amplifier of claim 2, wherein the first current mirror comprises a third transistor and a fourth transistor, the first terminal of the third transistor and the first terminal of the fourth transistor being coupled to a supply voltage, the control terminal of the third transistor, the second terminal of the third transistor, the control terminal of the fourth transistor being coupled to the first current mirror, the second terminal of the fourth transistor being coupled to the control terminal of the first transistor.
4. 4. The operational amplifier of claim 1, wherein the second current cell comprises a second current mirror and a second current source, the second current mirror being coupled to the second current source and the second node.
5. 5. The operational amplifier of claim 4, wherein the second current mirror comprises a fifth transistor and a sixth transistor, the first terminal of the fifth transistor and the first terminal of the sixth transistor being coupled to a supply voltage, the control terminal of the fifth transistor, the second terminal of the fifth transistor, the control terminal of the sixth transistor being coupled to the second current mirror, the second terminal of the sixth transistor being coupled to the second node.
6. 6. The operational amplifier of claim 1, wherein the bias unit comprises a first diode and a second diode, the anode of the first diode being coupled to the first node, the anode of the second diode being coupled to the cathode of the first diode, and the cathode of the second diode being coupled to the second node.
7. 7. The operational amplifier of claim 1, wherein the control unit comprises a seventh transistor, a second terminal of the seventh transistor being coupled to the control terminal of the second transistor, a first terminal of the seventh transistor being coupled to the ground voltage, and a control terminal of the seventh transistor being coupled to a previous stage of the output stage to receive the control signal.
8. 8. The operational amplifier of claim 1, wherein the output stage further comprises a first resistor and a second resistor, the first terminal of the first resistor being coupled to the first terminal of the first transistor, the first terminal of the second resistor being coupled to the first terminal of the second transistor, the second terminal of the first resistor being coupled to the second terminal of the second resistor to form the output terminal of the operational amplifier.
9. 9. The operational amplifier of claim 1 wherein the first transistor and the second transistor are transistors.
10. 10. A chip comprising an operational amplifier according to any one of claims 1 to 9.

Description

Operational amplifier and chip Technical Field The utility model belongs to the technical field of integrated circuits, and particularly relates to an operational amplifier and a chip. Background The output stage of most triode (bipolar junction transistor) op amps will employ a complementary emitter follower as shown in fig. 1. The triode Q3 and the triode Q4 are used as PNP current mirrors to provide current (the current mirror proportion is 1:m), the forward output current is provided by the NPN triode Q1, the reverse output current is provided by the PNP triode Q2, and the base electrode of the triode Q5 is connected with the output of the front stage. When no signal is output (i.e. the output current is zero), and thus the emitter currents flowing through transistor Q3 and transistor Q4 are equal Wherein V BE_Q1 and V BE_Q2 represent base-emitter voltages of the transistor Q1 and the transistor Q2, respectively, V D1 and V D2 represent forward turn-on voltages of the diode D1 and the diode D2, respectively, and R 1 and R 2 represent resistance values of the first resistor R1 and the second resistor R2, respectively. Most operational amplifiers have an R 1+R2 of the order of about 10 Ω -100 Ω, with no-load currents on the order of hundreds of uA-several mA. When the output stage operates in the high common mode condition, the voltage of the first node a is V OUT+I*R1+VBE_Q1, and when the voltage drop of the first resistor R1 is ignored, the voltage of the first node a is vout+v BE_Q1. The current mirror formed by the triode Q3 and the triode Q4 needs to ensure that the emitter-collector voltage V EC_Q4 (emitter-collector) of the triode Q4 needs to be larger than a certain threshold Vmarg to ensure that the current mirror works normally, that is, the collector outflow current of the triode Q4 is m×i1 (ignoring the influence of the small amplification factor beta and the base width modulation early effect), if the output voltage VOUT becomes large, the V EC_Q4 is smaller than Vmarg, the collector current of the triode Q4 can be smaller than m×i1 and even no current is provided, and the triode Q3 and the triode Q4 cannot provide correct current, so that the circuit function is abnormal. Thus, the output voltage V OUT under the configuration of FIG. 1 is AVDD-Vmarg-V BE_Q1 at the highest voltage with proper function, which is limited in some high common mode op amp applications. The information disclosed in this background section is only for enhancement of understanding of the general background of the utility model and should not be taken as an acknowledgement or any form of suggestion that this information forms the prior art already known to a person of ordinary skill in the art. Disclosure of utility model The utility model aims to provide an operational amplifier and a chip, which can improve the robustness of a circuit under a high common mode operation condition. In order to achieve the above purpose, the technical scheme includes that the operational amplifier comprises an output stage, wherein the output stage comprises a first transistor, a second transistor, a biasing unit, a first current unit, a second current unit and a control unit, the first current unit is connected with a control end of the first transistor to form a first node, the control unit is connected with a control end of the second transistor to form a second node, the biasing unit is connected with the first node and the second node, a second end of the first transistor is connected with a power supply voltage, a second end of the second transistor is connected with a ground voltage, a first end of the first transistor is connected with a first end of the second transistor to form an output end of the operational amplifier, and the second current unit is connected with the second node to inject current into the second node. In one or more embodiments of the present utility model, the first current unit includes a first current mirror and a first current source, and the first current mirror is connected to the first current source and a control terminal of the first transistor. In one or more embodiments of the present utility model, the first current mirror includes a third transistor and a fourth transistor, a first terminal of the third transistor and a first terminal of the fourth transistor are connected to a power supply voltage, a control terminal of the third transistor, a second terminal of the third transistor, and a control terminal of the fourth transistor are connected to the first current mirror, and a second terminal of the fourth transistor is connected to a control terminal of the first transistor. In one or more embodiments of the present utility model, the second current unit includes a second current mirror and a second current source, the second current mirror being connected to the second current source and a second node. In one or more embodiments of the present utility model, the second current mirror incl