CN-224233655-U - DC offset suppression circuit and variable gain amplifier

CN224233655UCN 224233655 UCN224233655 UCN 224233655UCN-224233655-U

Abstract

The utility model discloses a direct current offset suppression circuit and a variable gain amplifier, and belongs to the technical field of integrated circuits. In the direct current offset suppression circuit, a bias current module provides bias current for an input stage differential pair module, the input stage differential pair module receives and converts a differential input voltage signal into a first differential current signal to be output to a differential output end, and a feedback input stage differential pair module converts a differential feedback voltage signal output by a low-pass filter circuit into a second differential current signal to be output to the differential output end. In the direct current offset suppression circuit provided by the utility model, the bias current is only utilized by the input stage differential pair module, so that the current utilization rate can be effectively improved.

Inventors

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Assignees

本源量子计算科技（合肥）股份有限公司

Dates

Publication Date: 20260512
Application Date: 20250430

Claims (10)

1. The direct current offset suppression circuit is characterized by comprising a low-pass filter circuit and a direct current offset subtraction circuit, wherein the direct current offset subtraction circuit comprises a bias current module, an input stage differential pair module, a feedback input stage differential pair module and a common mode feedback module; The bias current module is used for providing bias current for the input stage differential module according to a first bias signal; the input stage differential pair module is used for converting a received differential input voltage signal into a first differential current signal which is output to a differential output end; The feedback input stage differential pair module is used for converting the differential feedback voltage signal output by the low-pass filter circuit into a second differential current signal output to the differential output end; and the common mode feedback module is used for detecting an output signal formed by the first differential current signal and the second differential current signal and enabling the output signal to be adjusted to be a target common mode signal.
2. The direct current offset rejection circuit of claim 1, wherein the bias current module comprises a first NMOS transistor having a source coupled to ground, a gate coupled to receive the first bias signal, and a drain coupled to provide the bias current.
3. The dc offset rejection circuit of claim 1, the input stage differential pair module comprising a second NMOS transistor and a third NMOS transistor; The source electrode of the second NMOS tube and the source electrode of the third NMOS tube are connected with the output end of the bias current module; The grid electrode of the second NMOS tube is used for receiving an inverted input signal in the differential input voltage signal, and the grid electrode of the third NMOS tube is used for receiving a non-inverting input signal in the differential input voltage signal; the drain electrode of the second NMOS tube is connected with the positive phase output end of the differential output end, and the drain electrode of the third NMOS tube is connected with the negative phase output end of the differential output end.
4. The dc offset suppression circuit of claim 3, wherein the second NMOS transistor and the third NMOS transistor are transistors having equal channel width to length ratios.
5. The direct current offset rejection circuit of claim 1, wherein the feedback input stage differential pair of modules comprises a first PMOS transistor and a second PMOS transistor, and the common mode feedback module comprises a third PMOS transistor, a fourth PMOS transistor, a first resistor, a second resistor, and a first operational amplifier; the grid electrode of the first PMOS tube and the grid electrode of the second PMOS tube are used for receiving a second bias signal; The drain electrode of the first PMOS tube is connected with the positive phase output end of the differential output end, and the drain electrode of the second PMOS tube is connected with the negative phase output end of the differential output end; The substrate of the first PMOS tube is used for receiving a positive feedback signal and a negative feedback signal in the differential feedback voltage signal; the substrate of the second PMOS tube is used for receiving a negative feedback signal in the differential feedback voltage signal; The source electrode of the first PMOS tube, the source electrode of the second PMOS tube and the drain electrode of the third PMOS tube are connected with the drain electrode of the fourth PMOS tube; The first end of the first resistor is connected to the positive phase output end, the second end of the first resistor is connected to the first end of the second resistor, and the second end of the second resistor is connected to the negative phase output end; The source electrode of the third PMOS tube and the source electrode of the fourth PMOS tube are connected with a power supply; The grid electrode of the fourth PMOS tube receives a third bias signal; the negative phase input end of the first operational amplifier is used for receiving the target common mode signal, the positive phase input end of the first operational amplifier is connected with the second end of the first resistor, and the output end of the first operational amplifier is connected with the grid electrode of the third PMOS tube.
6. The dc offset suppression circuit of claim 5, wherein the first PMOS transistor and the second PMOS transistor are transistors having equal channel width to length ratios.
7. The direct current offset suppression circuit of claim 5, wherein the first resistor and the second resistor have equal resistance values.
8. The dc offset rejection circuit of claim 1, wherein the low pass filter circuit comprises a first resistor, a second operational amplifier, a first capacitance, and a second capacitance; A first end of the first resistor receives a negative phase output signal of the variable gain amplifier, and a second end of the first resistor is connected with a positive phase input end of the second operational amplifier; The first end of the second resistor receives a positive phase output signal of the variable gain amplifier, and the second end of the second resistor is connected with a negative phase input end of the second operational amplifier; The first end of the first capacitor is connected with the non-inverting input end of the second operational amplifier, and the second end of the first capacitor is connected with the non-inverting output end of the second operational amplifier; the first end of the second capacitor is connected with the negative phase input end of the second operational amplifier, and the second end of the second capacitor is connected with the negative phase output end of the second operational amplifier.
9. A variable gain amplifier comprising the dc offset rejection circuit of any one of claims 1 to 8.
10. The variable gain amplifier of claim 9, further comprising a variable gain amplification unit; the differential input end of the variable gain amplifying unit is connected with the differential output end of the direct current offset subtracting circuit in the direct current offset restraining circuit, and the differential output end of the variable gain amplifying unit is connected with the differential input end of the low-pass filter circuit in the direct current offset restraining circuit.

Description

DC offset suppression circuit and variable gain amplifier Technical Field The utility model belongs to the field of integrated circuits, and particularly relates to a direct current offset suppression circuit and a variable gain amplifier. Background In wireless local area networks and worldwide interoperability for microwave access receivers, variable gain amplifiers (VGAs; variable GAIN AMPLIFIER) are required to provide high gain (e.g., 60dB or even higher). However, the direct current offset generated at the output end of the mixer can cause saturation of the output end after being amplified by the VGA, and the normal operation of the subsequent module is affected. Thus, a direct current imbalance suppression (DCOC; DC-Offset Cancellation) technique is required. In the prior art, as shown in fig. 1, a Low-pass filter (LPF; low-PASS FILTER) feedback network composed of a dc offset subtraction circuit may be introduced to indirectly implement dc offset suppression. As shown in fig. 2, a pair of input differential pairs is added in the existing dc offset subtraction circuit as a transconductance stage of the dc offset suppression feedback loop to realize superposition of the input stage current and the feedback stage current, however, in the case of tail current determination, the transconductance is reduced due to current reduction of the input stage differential pair, which has the problem of low current utilization efficiency. Therefore, how to improve the current utilization efficiency of the dc offset suppression circuit is a problem to be solved. Disclosure of utility model The utility model aims to provide a direct current offset suppression circuit and a variable gain amplifier, which are used for solving the defects in the prior art and improving the current utilization efficiency of the direct current offset suppression circuit. The exemplary embodiment of the present application is implemented as follows. In a first aspect, an example of the present application provides a dc offset rejection circuit, including a low-pass filter circuit and a dc offset subtraction circuit, where the dc offset subtraction circuit includes a bias current module, an input stage differential pair module, a feedback input stage differential pair module, and a common mode feedback module: The bias current module is used for providing bias current for the input stage differential module according to a first bias signal; the input stage differential pair module is used for converting a received differential input voltage signal into a first differential current signal which is output to a differential output end; The feedback input stage differential pair module is used for converting the differential feedback voltage signal output by the low-pass filter circuit into a second differential current signal output to the differential output end; and the common mode feedback module is used for detecting an output signal formed by the first differential current signal and the second differential current signal and enabling the output signal to be adjusted to be a target common mode signal. According to some examples of the application, the bias current module includes a first NMOS transistor having a source connected to ground, a gate for receiving the first bias signal, and a drain for providing the bias current. According to some examples of the application, the input stage differential pair module includes a second NMOS transistor and a third NMOS transistor; The source electrode of the second NMOS tube and the source electrode of the third NMOS tube are connected with the output end of the bias current module; The grid electrode of the second NMOS tube is used for receiving an inverted input signal in the differential input voltage signal, and the grid electrode of the third NMOS tube is used for receiving a non-inverting input signal in the differential input voltage signal; the drain electrode of the second NMOS tube is connected with the positive phase output end of the differential output end, and the drain electrode of the third NMOS tube is connected with the negative phase output end of the differential output end. According to some examples of the application, the second NMOS transistor and the third NMOS transistor are transistors having equal channel width to length ratios. According to some examples of the application, the feedback input stage differential module comprises a first PMOS tube and a second PMOS tube, and the common mode feedback module comprises a third PMOS tube, a fourth PMOS tube, a first resistor, a second resistor and a first operational amplifier; the grid electrode of the first PMOS tube and the grid electrode of the second PMOS tube are used for receiving a second bias signal; The drain electrode of the first PMOS tube is connected with the positive phase output end of the differential output end, and the drain electrode of the second PMOS tube is connected with the negative phase output en