CN-224233673-U - Maximum pulse width limiting circuit based on DQ trigger and logic gate

Abstract

The application relates to the technical field of energy storage, in particular to a maximum pulse width limiting circuit based on a DQ trigger and a logic gate, which comprises the DQ trigger, a logic AND gate circuit and an RC circuit; the clock end of the DQ trigger is connected with the PWM generator, the data end D and the set end Sn of the DQ trigger are connected with a fixed high level, and the negative output pin Qn and the reset pin Rn of the DQ trigger are connected to the RC circuit. The maximum pulse width limitation is directly realized through hardware logic, and the problems of high response delay and dependence on software reliability in the prior art are solved by utilizing the rising edge detection characteristic of the DQ trigger, the charge-discharge characteristic of the RC network and the real-time comparison function of the logic gate without software intervention.

Inventors

• WEI JIANSHENG
• LI JINZHOU
• XIE XIAOKUN

Assignees

• 惠州市乐亿通科技股份有限公司

Dates

Publication Date

20260512

Application Date

20250610

Claims (9)

1. 1. The maximum pulse width limiting circuit based on the DQ trigger and the logic gate is characterized by comprising the DQ trigger, a logic AND gate circuit and an RC circuit; the clock end of the DQ trigger is connected with a PWM generator; The data end D and the set end Sn of the DQ trigger are connected with a fixed high level; the negative output pin Qn and the reset pin Rn of the DQ flip-flop are connected to an RC circuit.
2. 2. The maximum pulse width limiting circuit based on the DQ trigger and the logic gate as claimed in claim 1, wherein the output port Q of the DQ trigger is connected with a logic AND gate circuit, and the other end of the logic AND gate circuit is connected with a PWM generator.
3. 3. A maximum pulse width limiting circuit based on DQ flip-flops and logic gates as defined in claim 2, The negative output pin Qn of the DQ flip-flop is connected to the resistor R1 of the RC circuit.
4. 4. A maximum pulse width limiting circuit based on DQ flip-flops and logic gates as defined in claim 3, The reset pin Rn of the DQ trigger is connected to the capacitor C1 of the RC circuit; The reset pin Rn is also connected with the other end of the resistor R1.
5. 5. The maximum pulse width limiting circuit according to any one of claims 1-4, wherein the data terminal D, the set terminal Sn, and the output port Q output a high level when the DQ flip-flop receives the input PWM signal rising to the trigger value, the negative output pin Qn outputs a low level, and the negative output pin Qn low level causes the RC circuit to start discharging the capacitor C1.
6. 6. The maximum pulse width limiting circuit based on DQ flip-flop and logic gate as recited in claim 5, wherein said capacitor C1 discharge time is a maximum pulse width time, said maximum pulse width time being set by adjusting R1 resistance and C1 capacitance.
7. 7. The maximum pulse width limiting circuit based on DQ flip-flop and logic gates of claim 6 wherein said logic and gate compares the input PWM signal with a reference maximum pulse width signal and outputs a trimmed PWM signal.
8. 8. The maximum pulse width limiting circuit based on DQ flip-flop and logic gate as recited IN claim 7, wherein the logic AND gate output signal is the input PWM signal when the PWM_IN pulse width of the input PWM signal is less than or equal to the PWM_MAX pulse width of the reference maximum pulse width signal.
9. 9. The maximum pulse width limiting circuit based on DQ flip-flop and logic gate according to claim 7, wherein when pwm_in pulse width of input PWM signal > pwm_max pulse width of reference maximum pulse width signal, the logic and gate forces output low level at the exceeding threshold part, limiting pulse width to reference maximum pulse width signal.

Description

Maximum pulse width limiting circuit based on DQ trigger and logic gate Technical Field The application belongs to the technical field of energy storage, and particularly relates to a maximum pulse width limiting circuit based on a DQ trigger and a logic gate. Background In a switching power supply topology, a circuit such as Boost, buck, flyback, the limitation of the maximum duty cycle is one of the key factors for ensuring the safe and stable operation of the circuit. The duty cycle refers to the ratio of the on time of a switching tube to the whole period, and directly influences the efficiency of power conversion and the stability of a circuit. If the duty cycle exceeds the design threshold, a series of adverse consequences may result, including over-voltage, over-heating of the power device, saturation of the magnetic device, and eventual damage. Currently, many switching power supply systems employ a control scheme based on software algorithms and a processor to regulate and limit the maximum duty cycle. These systems typically rely on multiple steps of signal sampling, algorithm computation, instruction execution, etc. to dynamically adjust the duty cycle to accommodate load variations. However, this approach has certain drawbacks. When the load changes rapidly, the system needs to undergo multiple processes such as signal sampling, calculation processing and instruction execution, and the response delay is high. Such delays may cause the duty cycle to exceed the design threshold for a short period of time, thereby creating unsafe operating conditions. In addition, the method based on software control has the problems of programming and maintaining. If the software algorithm has defects or the digital chip has abnormality, the duty ratio limiting function may be invalid, and the safe operation of the circuit cannot be ensured. In this case, the circuit may face serious problems such as overvoltage, overheat, etc., and may even cause damage to the power device. Therefore, the prior art is faced with how to control the maximum duty cycle rapidly and accurately under the condition of dynamic load variation so as to ensure the stability and the safety of the switching power supply system. For this reason, a more efficient, reliable and low-latency duty cycle control method is needed to avoid the drawbacks of the existing software control schemes. Disclosure of utility model The application provides a maximum pulse width limiting circuit based on a DQ trigger and a logic gate, which directly realizes maximum pulse width limitation through hardware logic and solves the problems of high response delay and dependence on software reliability in the prior art by utilizing the rising edge detection characteristic of the DQ trigger, the charge-discharge characteristic of an RC network and the real-time comparison function of the logic gate without software intervention. The maximum pulse width limiting circuit based on the DQ trigger and the logic gate comprises the DQ trigger, a logic AND gate circuit and an RC circuit. Wherein, each module mainly functions as: DQ flip-flop, which detects the rising edge of the input PWM signal to generate a status signal. And the logic AND circuit compares the input PWM signal with a reference maximum pulse width signal (PWM MAX) and outputs a trimmed PWM signal. And the RC network is matched with the reset pin Rn of the DQ trigger to generate a reference maximum pulse width signal. Preferably, a clock end of the DQ trigger is connected with the PWM generator. Preferably, the data terminal D and the set terminal Sn of the DQ flip-flop are connected to a fixed high level, so as to ensure that the state flip is triggered only at the rising edge of the clock. Preferably, the negative output pin Qn and the reset pin Rn of the DQ flip-flop are connected to an RC circuit. Preferably, an output port Q of the DQ trigger is connected with a logic AND gate circuit, and the other end of the logic AND gate circuit is connected with a PWM generator. Preferably, the negative output pin Qn of the DQ flip-flop is connected to the resistor R1 of the RC circuit. Preferably, the reset pin Rn of the DQ flip-flop is connected to the capacitor C1 of the RC circuit; further, the reset pin Rn is also connected to the other end of the resistor R1. Preferably, when the DQ flip-flop receives the input PWM signal rising to the trigger value, the data terminal D, the set terminal Sn, and the output port Q output a high level, the negative output pin Qn outputs a low level, and the negative output pin Qn low level causes the RC circuit to start discharging the capacitor C1. Preferably, the discharging time of the capacitor C1 is a maximum pulse width time, and the maximum pulse width time can be set by adjusting the R1 resistance value and the C1 capacitance value. Preferably, the discharging time of the capacitor C1 is a maximum pulse width time, and the maximum pulse width time can be set by adjusting t