CN-224233677-U - Chip pin multiplexing circuit, chip and electronic equipment

CN224233677UCN 224233677 UCN224233677 UCN 224233677UCN-224233677-U

Abstract

The utility model provides a chip pin multiplexing circuit which comprises a multiplexing pin, a pull-up circuit, a pull-down circuit, a control end, a double-threshold comparison circuit and an output control circuit, wherein one end of the multiplexing pin is coupled with the pull-up circuit, the pull-down circuit and a third detection circuit, the other end of the multiplexing pin is coupled with an external MCU, one end of the pull-up circuit is coupled with the multiplexing pin, the other end of the pull-up circuit is connected with an internal voltage for providing a weak pull-up level, one end of the pull-down circuit is coupled with the multiplexing pin, the other end of the pull-down circuit is grounded, the control end of the pull-down circuit is connected with a fault signal for providing a low level based on the fault signal, the double-threshold comparison circuit is internally provided with a preset double threshold, the input end of the pull-down circuit is coupled with the multiplexing pin, and the output control circuit is coupled with the output control signal based on the level of the multiplexing pin and the double threshold. The utility model integrates the enabling control, fault detection and fault recovery configuration into a single pin by multiplexing the same pin, reduces the number of internal elements, effectively reduces the occupied PCB area and pin number, reduces the chip packaging size and effectively reduces the cost.

Inventors

LEI WENHAO
ZHOU ZONGJIE
YE JUN
LIAO JIANPING

Assignees

厦门市必易微电子技术有限公司

Dates

Publication Date: 20260512
Application Date: 20250430

Claims (11)

1. A chip pin multiplexing circuit, comprising: one end of the multiplexing pin is coupled with the pull-up circuit, the pull-down circuit and the third detection circuit, and the other end of the multiplexing pin is coupled with the external MCU; One end of the pull-up circuit is coupled with the multiplexing pin, and the other end of the pull-up circuit is connected with an internal voltage and is used for providing a weak pull-up level; One end of the pull-down circuit is coupled with the multiplexing pin, the other end of the pull-down circuit is grounded, and the control end is connected with a fault signal and is used for providing a low level based on the fault signal; the dual-threshold comparison circuit is internally provided with a preset dual threshold, the input end of the dual-threshold comparison circuit is coupled with the multiplexing pin, and the output end of the dual-threshold comparison circuit is coupled with the output control circuit and is used for outputting control signals based on the level of the multiplexing pin and the dual threshold.
2. The chip pin multiplexing circuit of claim 1, wherein the pull-up circuit comprises: And one end of the pull-up resistor is coupled with the multiplexing pin, and the other end of the pull-up resistor is coupled with the internal voltage.
3. The chip pin multiplexing circuit of claim 2, wherein the pull-up resistor has a resistance of 2mΩ±25%.
4. The chip pin multiplexing circuit according to claim 1 or 2, wherein the internal voltage is 2.1-3.5 v.
5. The chip pin multiplexing circuit of claim 1, wherein the pull-down circuit comprises: and the drain electrode of the switching tube is coupled with the multiplexing pin, the source electrode of the switching tube is grounded, and the grid electrode of the switching tube is coupled with the fault signal detection circuit and is used for being turned on based on the first state of the fault signal and turned off based on the second state of the fault signal.
6. The chip pin multiplexing circuit of claim 5, wherein the fault signal detection circuit comprises: And the first input end of the OR gate is connected with the under-voltage fault signal, the second input end of the OR gate is connected with the short-circuit fault signal, and the output end of the OR gate is coupled with the grid electrode of the switching tube.
7. The chip pin multiplexing circuit of claim 5, wherein the switching tube is an NMOS transistor.
8. The chip pin multiplexing circuit of claim 1, wherein the dual threshold comparison circuit comprises: The input end of the Schmitt trigger is coupled with the multiplexing pin, and the output end of the Schmitt trigger is coupled with the output control circuit and is used for outputting a control signal based on the level of the multiplexing pin.
9. The chip pin multiplexing circuit of claim 8, wherein the schmitt trigger has a first threshold voltage of 2.1V ± 5%, a second threshold voltage of 1.0V ± 5%, and a hysteresis voltage window ∈1.1V ± 0.05V.
10. A chip comprising the chip pin multiplexing circuit of any one of claims 1-9.
11. An electronic device comprising the chip of claim 10.

Description

Chip pin multiplexing circuit, chip and electronic equipment Technical Field The present utility model relates to the field of electronics, and in particular, but not exclusively, to a chip pin multiplexing circuit, a chip and an electronic device. Background As shown in FIG. 1, the enable control, fault detection and fault recovery configuration circuit in the prior art forces the chip to turn off the output when the external level is pulled down, and enables the chip output when the external level is high. The FAULT pin is pulled up through an external resistor to form an open drain NMOS structure in the FAULT pin, the open drain NMOS structure is opened when a FAULT is identified, the FAULT pin is pulled down forcibly, and an external MCU detects the falling edge of the FAULT pin to judge whether the FAULT occurs. The RCIN pin charges to the schmitt trigger threshold after the fault clears through the external RC network to re-enable the output. The application scene of the enabling control, fault detection and fault recovery configuration circuit is shown in fig. 2, and the chip integrates a three-phase high-voltage half-bridge drive, dead time, UVLO, over-current protection OCP, an externally adjustable protection clearing circuit and the like. Three pins are needed to be adopted in one chip to realize the functions of enabling control, FAULT detection and FAULT recovery respectively, internal components are repeated, for example, the FAULT pin and the RCIN pin are respectively connected with an open-drain NMOS structure, the RCIN pin and the EN pin are respectively connected with a Schmitt trigger, so that the size and the PCB area of the chip are increased, and the cost of the chip is increased. In view of this, there is a need to provide a new architecture or control method in order to solve at least some of the above problems. Disclosure of utility model At least aiming at one or more problems in the background art, the utility model provides a chip pin multiplexing circuit, which integrates enabling control, fault detection and fault recovery configuration into a single pin through multiplexing of the same pin, reduces the number of internal elements, effectively reduces occupied PCB area and pin number, reduces the chip packaging size and effectively reduces the cost. According to one aspect of the utility model, a chip pin multiplexing circuit comprises: one end of the multiplexing pin is coupled with the pull-up circuit, the pull-down circuit and the third detection circuit, and the other end of the multiplexing pin is coupled with the external MCU; One end of the pull-up circuit is coupled with the multiplexing pin, and the other end of the pull-up circuit is connected with an internal voltage and is used for providing a weak pull-up level; One end of the pull-down circuit is coupled with the multiplexing pin, the other end of the pull-down circuit is grounded, and the control end is connected with a fault signal and is used for providing a low level based on the fault signal; the dual-threshold comparison circuit is internally provided with a preset dual threshold, the input end of the dual-threshold comparison circuit is coupled with the multiplexing pin, and the output end of the dual-threshold comparison circuit is coupled with the output control circuit and is used for outputting control signals based on the level of the multiplexing pin and the dual threshold. Optionally, the pull-up circuit comprises a pull-up resistor, one end of which is coupled with the multiplexing pin, and the other end of which is coupled with the internal voltage. Optionally, the resistance value of the pull-up resistor is 2MΩ+ -25%. Optionally, the internal voltage is 2.1-3.5 v. Optionally, the pull-down circuit comprises a switch tube, wherein the drain electrode of the switch tube is coupled with the multiplexing pin, the source electrode of the switch tube is grounded, the grid electrode of the switch tube is coupled with the fault signal detection circuit, and the switch tube is used for being turned on based on a first state of the fault signal and turned off based on a second state of the fault signal. Optionally, the fault signal detection circuit comprises an OR gate, wherein a first input end of the OR gate is connected with the undervoltage fault signal, a second input end of the OR gate is connected with the short circuit fault signal, and an output end of the OR gate is coupled with the grid electrode of the switching tube. Optionally, the switching transistor is an NMOS transistor. Optionally, the dual-threshold comparison circuit comprises a Schmitt trigger, wherein the input end of the Schmitt trigger is coupled with the multiplexing pin, and the output end of the Schmitt trigger is coupled with the output control circuit and is used for outputting a control signal based on the level of the multiplexing pin. Optionally, the first threshold voltage of the schmitt trigger is 2.1 v+5%, the second thr