CN-224233700-U - Device for synchronizing data input signals and clock input signals

Abstract

The present disclosure provides an apparatus for synchronizing a data input signal and a clock input signal. The apparatus includes a receiving circuit, a processing circuit, and a transmitting circuit. The receiving circuit generates a clock input signal and includes a plurality of receivers, each of which receives a data input signal and generates a first data output signal. Each receiver includes a delay line that does not include a duty cycle corrector (duty cycle corrector, DCC), the delay line having a predetermined number of delay elements and introducing a propagation delay to the data input signal by a fixed amount that substantially matches the propagation delay of the clock input signal. The processing circuit processes the first data output signal and generates a second data output signal. The transmission circuit transmits the second data output signal to a data signal receiving device.

Inventors

• HUANG YUJIE
• LIN MUSHAN
• GUO XINHONG
• CAI JIANQUN

Assignees

• 台湾积体电路制造股份有限公司

Dates

Publication Date

20260512

Application Date

20250324

Priority Date

20240422

Claims (10)

1. 1. An apparatus for synchronizing a data input signal and a clock input signal, the apparatus comprising: A receiving circuit configured to generate the clock input signal and comprising a plurality of receivers, each receiver configured to receive the data input signal and to generate a first data output signal, wherein each receiver comprises a first delay line that does not include a duty cycle corrector, has a predetermined number of delay components, and is configured to introduce a propagation delay to the data input signal through a fixed amount that substantially matches the propagation delay of the clock input signal; A processing circuit configured to process the first data output signal and generate a second data output signal, and A transmission circuit configured to transmit the second data output signal to a data signal receiving device.
2. 2. The apparatus of claim 1, further comprising a data input/output circuit configured to receive the data input signal and the clock input signal and to generate high and low portions of the data input signal on rising and falling edges of the clock input signal.
3. 3. The apparatus of claim 1, further comprising a second delay line configured to fine tune a propagation delay of the first delay line.
4. 4. The apparatus of claim 3, wherein the second delay line is configured to receive a control input signal and to introduce an amount of propagation delay that varies with the control input signal.
5. 5. The apparatus of claim 4, further comprising a clock tree, comprising: A correction circuit configured to correct a duty cycle of the first clock input signal and generate a second clock input signal having a duty cycle of approximately 50%; A distribution network configured to generate a plurality of third clock input signals based on the second clock input signals, and A control signal generation circuit configured to generate the control input signal.
6. 6. The apparatus of claim 5, wherein the control signal generation circuit comprises: a first delay line configured to introduce a propagation delay to the first clock input signal; A second delay line configured to fine tune a propagation delay of the first delay line; a phase detector configured to compare a phase of the first clock input signal and a phase of the second clock input signal and generate a phase difference based on a result of the comparison, and A controller configured to generate a control input signal based on the phase difference.
7. 7. An apparatus for synchronizing a data input signal and a clock input signal, the apparatus comprising: A receiving circuit comprising a receiver configured to receive a data input signal and to generate the clock input signal and a first data output signal, wherein the receiver comprises a delay line configured to receive a control input signal and to introduce a propagation delay to the data input signal through an amount of variation that varies with the control input signal and substantially matches the propagation delay of the clock input signal; A processing circuit configured to process the first data output signal and generate a second data output signal, and A transmission circuit configured to transmit the second data output signal to a data signal receiving device.
8. 8. The apparatus of claim 7, further comprising a clock tree configured to receive a first clock input signal and to generate a second clock input signal, and comprising a control signal generation circuit configured to generate the control input signal based on the first clock input signal and the second clock input signal.
9. 9. The apparatus of claim 7, further comprising a clock tree, the clock tree comprising: A correction circuit configured to correct a duty cycle of the first clock input signal and generate a second clock input signal having a duty cycle of approximately 50%, and A distribution network configured to generate a plurality of third clock input signals from the second clock input signals.
10. 10. The apparatus of claim 7, further comprising a clock tree, the clock tree comprising: A correction circuit configured to correct a phase error between the first clock input signal and the second clock input signal, and A distribution network configured to generate a plurality of third clock input signals based on the first clock input signal and the second clock input signal.

Description

Device for synchronizing data input signals and clock input signals Technical Field The present disclosure relates to an apparatus, and more particularly, to an apparatus for synchronizing a data input signal and a clock input signal. Background Devices are typically configured to receive a data input signal from a data signal generating device and a clock input signal from a clock signal generating device, process the data input signal to generate a data output signal, and transmit the data output signal to a data signal receiving device. Synchronization within a device is often very important to the normal performance of such devices. Disclosure of utility model In one embodiment of the present disclosure, an apparatus for synchronizing a data input signal and a clock input signal includes a receiving circuit, a processing circuit, and a transmitting circuit. The receiving circuit generates a clock input signal. The receiving circuit includes a plurality of receivers, each receiver configured to receive a data input signal and generate a first data output signal. Each receiver includes a first delay line. The first delay line does not include a duty cycle corrector, has a predetermined number of delay elements, and introduces a propagation delay to the data input signal through a fixed amount. The fixed amount substantially matches the propagation delay of the clock input signal. The processing circuit processes the first data output signal and generates a second data output signal. The transmission circuit transmits the second data output signal to the data signal receiving device. In one embodiment of the present disclosure, an apparatus for synchronizing a data input signal and a clock input signal includes a receiving circuit, a processing circuit, and a transmitting circuit. The receiving circuit includes a receiver. The receiver receives a data input signal and generates a clock input signal and a first data output signal. The receiver includes a delay line. The delay line is configured to receive the control input signal and to introduce a propagation delay to the data input signal through the amount of variation. The amount of change varies with the control input signal and substantially matches the propagation delay of the clock input signal. The processing circuit processes the first data output signal and generates a second data output signal. The transmission circuit transmits the second data output signal to the data signal receiving device. Drawings Aspects of the disclosure may be best understood when read with the following detailed description in conjunction with the accompanying drawings: FIG. 1A is a block diagram of an exemplary embodiment of an apparatus according to an embodiment of the present disclosure; FIG. 1B is a timing diagram illustrating an exemplary embodiment of a relationship between a data input signal and a clock input signal, according to an embodiment of the present disclosure; FIG. 2A is a block diagram of a first exemplary embodiment of a receive circuit of a device according to one embodiment of the present disclosure; FIG. 2B is another timing diagram illustrating an exemplary embodiment of a relationship between a data input signal and a clock input signal according to an embodiment of the present disclosure; FIG. 3 is a flowchart of a first exemplary embodiment of a method for synchronizing a data input signal and a clock input signal, in accordance with an embodiment of the present disclosure; FIG. 4 is a block diagram of a second exemplary embodiment of a receive circuit of a device according to an embodiment of the present disclosure; FIG. 5 is a flowchart of a second exemplary embodiment of a method for synchronizing a data input signal and a clock input signal, in accordance with an embodiment of the present disclosure; FIG. 6 is a block diagram of a third exemplary embodiment of a receive circuit of a device according to an embodiment of the present disclosure; FIG. 7 is a flowchart of a third exemplary embodiment of a method for synchronizing a data input signal and a clock input signal, in accordance with an embodiment of the present disclosure; FIG. 8 is a block diagram of a fourth exemplary embodiment of a receive circuit of a device according to an embodiment of the present disclosure; FIG. 9 is a flowchart of a fourth exemplary embodiment of a method for synchronizing a data input signal and a clock input signal, according to an embodiment of the present disclosure; FIG. 10 is a block diagram of a fifth exemplary embodiment of a receive circuit of an apparatus in accordance with an embodiment of the present disclosure, and FIG. 11 is a flowchart of a fifth exemplary embodiment of a method for synchronizing a data input signal and a clock input signal, in accordance with an embodiment of the present disclosure. Description of the reference numerals 100:Device 110 Receiving circuit 120 Processing circuit 130 Transmission circuit 210 Clock tree 220 Rece