CN-224233907-U - Chip pin leading-out structure and liquid crystal writing device

Abstract

The utility model discloses a chip pin leading-out structure and a liquid crystal writing device, which comprise a chip to be led out and an FPC circuit board, wherein the FPC circuit board comprises a first end and a second end, the second end is provided with at least two rows of bonding pads which are arranged along an arc shape, and the bonding pads which are arranged along the arc shape are arranged in a staggered manner. The chip pin extraction structure can lead out the dense pins of the chip by wire bonding without hard packaging the chip, ensures reliable connection between the chip and the bonding pads, and greatly reduces the production cost of products.

Inventors

• LI QINGBO
• YANG MENGXUN
• ZHOU SHENGGANG

Assignees

• 山东蓝贝易书信息科技有限公司

Dates

Publication Date

20260512

Application Date

20250422

Claims (9)

1. 1. The chip pin leading-out structure is characterized by comprising a chip to be led out and an FPC circuit board, wherein the FPC circuit board comprises a first end and a second end, at least two rows of bonding pads which are arranged along an arc shape are arranged at the second end, and the bonding pads which are arranged along the arc shape are arranged in a staggered manner.
2. 2. The die pin extraction structure of claim 1, wherein the second end is provided with two rows of pads arranged along an arc.
3. 3. The chip pin extraction structure as claimed in claim 2, wherein pins of the chip to be extracted are sequentially wire-bonded with pads in the arc direction, and adjacent two pins are respectively connected with pads in different arc rows.
4. 4. The die pin extraction structure of claim 1, wherein the second end is provided with three rows of pads arranged along an arc.
5. 5. The chip pin extraction structure as claimed in claim 4, wherein pins of the chip to be extracted are sequentially wire-bonded with pads in the arc direction, and adjacent three pins are respectively connected with pads in different arc rows.
6. 6. A chip pin extraction structure according to any one of claims 1-5, characterized in that pins of the chip to be extracted are wire-bonded with corresponding pads on the FPC board by means of wire bonding.
7. 7. A chip pin extraction structure according to any one of claims 1 to 5, characterized in that said chip to be extracted is a liquid crystal driving chip.
8. 8. The chip pin out structure of claim 7, wherein the liquid crystal driving chip is an STN liquid crystal driving chip or a VFD driving chip.
9. 9. A liquid crystal writing device comprises a first conductive layer, a liquid crystal layer and a second conductive layer which are sequentially arranged, wherein the first conductive layer and the second conductive layer are respectively divided into a plurality of conductive areas which are mutually insulated; Pins of the liquid crystal driving chip corresponding to the first conductive layer are led out through the chip pin leading-out structure according to any one of claims 1-8 and are connected with the conductive area on the first conductive layer through the first end of the FPC circuit board; pins of the liquid crystal driving chip corresponding to the second conductive layer are led out through the chip pin leading-out structure according to any one of claims 1-8, and are connected with the conductive areas on the second conductive layer through the first end of the FPC circuit board.

Description

Chip pin leading-out structure and liquid crystal writing device Technical Field The utility model relates to the technical field of liquid crystal writing, in particular to a chip pin leading-out structure and a liquid crystal writing device. Background The statements in this section merely provide background information related to the present disclosure and may not necessarily constitute prior art. In order to realize the local erasing function of the liquid crystal writing device, the prior art divides the upper and lower ITO conductive layers of the liquid crystal writing device into a plurality of mutually insulated strip conductive areas, and voltage difference is formed between the upper and lower conductive areas by applying different voltages to each conductive area, so as to realize the local erasing. In the prior art, a liquid crystal driving chip (such as an STN liquid crystal driving chip or a VFD driving chip) is generally utilized to apply different voltages to each conductive area, and because pins of the liquid crystal driving chip are very dense, and the existing FPC pads are mostly in a single-row linear arrangement mode, if pins are directly connected with the FPC pads, short circuit phenomenon is often generated due to too small gaps between the pads. Therefore, the prior art needs to package a liquid crystal driving chip, dispose the packaged chip on an FPC, and then connect to respective conductive areas of upper and lower ITO conductive layers through the FPC. Alternatively, the pins of the liquid crystal driving chip may be connected to the conductive areas of the upper and lower ITO conductive layers by using a COF process. However, the above-mentioned processing methods all require packaging the liquid crystal driving chip, and the COF fixture has high cost and expensive unit price, which greatly increases the production cost of the product. Disclosure of utility model In order to solve the problems, the utility model provides a chip pin leading-out structure and a liquid crystal writing device, which are provided with a plurality of rows of FPC bonding pads in arc arrangement, wherein the rows of bonding pads are arranged in a staggered manner, chip pins are sequentially connected with bonding pads in wire bonding (wire bonding) in sequence, the distance between the FPC bonding pads can be increased, the phenomenon of short circuit caused by too small gap between the bonding pads is avoided, the chip is not required to be subjected to hard packaging, and the chip pins can be led out through the FPC bonding pads. In some embodiments, the following technical scheme is adopted: The chip pin extraction structure comprises a chip to be extracted and an FPC circuit board, wherein the FPC circuit board comprises a first end and a second end, at least two rows of bonding pads which are arranged along an arc shape are arranged at the second end, and the bonding pads which are arranged along the arc shape are arranged in a staggered manner. As a further scheme, the second end is provided with two rows of bonding pads distributed along an arc shape, pins to be led out of the chip are sequentially connected with bonding pads in the arc shape in a wire bonding mode, and two adjacent pins are respectively connected with bonding pads in different arc-shaped rows. Or the second end is provided with three rows of bonding pads distributed along the arc, pins of the chip to be led out are sequentially connected with the bonding pads in the arc direction in a wire bonding mode, and the adjacent three pins are respectively connected with the bonding pads in different arc rows. As a further scheme, the pins of the chip to be led out are connected with the corresponding bonding pads on the FPC circuit board in a wire bonding mode. As a further scheme, the chip to be led out is a liquid crystal driving chip. The liquid crystal driving chip is an STN liquid crystal driving chip or a VFD driving chip. In other embodiments, the following technical solutions are adopted: The liquid crystal writing device comprises a first conductive layer, a liquid crystal layer and a second conductive layer which are sequentially arranged, wherein the first conductive layer and the second conductive layer are respectively divided into a plurality of conductive areas which are mutually insulated; Pins of the liquid crystal driving chip corresponding to the first conductive layer are led out through the chip pin leading-out structure, and are connected with the conductive area on the first conductive layer through the first end of the FPC circuit board; Pins of the liquid crystal driving chip corresponding to the second conductive layer are led out through the chip pin leading-out structure, and are connected with the conductive area on the second conductive layer through the first end of the FPC circuit board. Compared with the prior art, the utility model has the beneficial effects that: (1) According to the utility model,