CN-224234102-U - Temporary carrier for transferring semiconductor device and packaging structure of semiconductor device

CN224234102UCN 224234102 UCN224234102 UCN 224234102UCN-224234102-U

Abstract

The utility model discloses a temporary carrier for transferring a semiconductor device and a packaging structure of the semiconductor device. The temporary carrier plate comprises a carrier plate and a peelable adhesive layer, the peelable adhesive layer comprises a plurality of transfer units, and the transfer units comprise a plurality of electrodes adhered to the top surface of the peelable adhesive layer. The packaging structure comprises a packaging body, an insulating layer, a wiring layer and a plurality of working electrodes, wherein the packaging body comprises packaging glue and a semiconductor device, the wiring layer is manufactured on a stripping surface of the packaging body and comprises a unit circuit, the unit circuit is connected with electrodes of the semiconductor device, the insulating layer covers the unit circuit and the electrodes of the semiconductor device, when the unit circuit is connected with the plurality of switching electrodes, the working electrodes are formed on the corresponding switching electrodes, when the packaging structure comprises electrode plates, the working electrodes are embedded in the electrode plates, and the working electrodes are connected with the unit circuit. The temporary carrier plate has the advantages of simple structure, good universality, good packaging structure universality of semiconductor devices and suitability for different types of semiconductor devices.

Inventors

HE ZHONGLIANG
ZHAO BIAO
LIU QINGDONG
RAO ZHENGGANG
WANG ZHIGUO

Assignees

江西鼎华芯泰科技有限公司

Dates

Publication Date: 20260512
Application Date: 20250521

Claims (9)

1. A temporary carrier plate for transferring semiconductor devices comprises a carrier plate and a strippable glue layer covering the top surface of the carrier plate, and is characterized in that the top surface of the strippable glue layer comprises a plurality of transfer units arranged in an array, the transfer units comprise transfer areas of the semiconductor devices, and the transfer units comprise a plurality of electrodes adhered to the top surface of the strippable glue layer.
2. The temporary carrier of claim 1, wherein the electrode is a transfer electrode that is the basis for forming the working electrode.
3. The temporary carrier plate according to claim 1, comprising an electrode plate, wherein the electrode plate comprises a substrate, the substrate comprises a substrate unit corresponding to the transfer unit, the substrate unit comprises a plurality of electrodes, the electrodes are embedded in holes of the substrate, and the bottom surface of the substrate is adhered to the top surface of the strippable glue layer.
4. The temporary carrier of claim 1, wherein the electrodes are working electrodes, the working electrodes comprise top electrodes and bottom electrodes, the top surfaces of the top electrodes are substantially flush with the top surface of the substrate, the bottom surfaces of the bottom electrodes are substantially flush with the bottom surface of the substrate, the substrate unit comprises chip transfer holes, and the chip transfer holes of the substrate unit surround the periphery of the transfer region on the top surface of the peelable glue layer.
5. The packaging structure of the semiconductor device comprises a packaging body, an insulating layer and a plurality of working electrodes, wherein the packaging body comprises packaging glue and the semiconductor device, and is characterized in that the bottom surface of the packaging body is a stripping surface, and electrodes of all the semiconductor device are exposed on the stripping surface; The package structure further includes: 1) When the unit circuit is connected with a plurality of switching electrodes, the insulating layer comprises a working electrode window corresponding to the switching electrodes, and the working electrode is formed in the working electrode window through electroplating metal and is connected with the corresponding switching electrode; 2) When the packaging structure comprises an electrode plate, the working electrode is embedded in the electrode plate, the working electrode is connected with the unit circuit, the top surface of the working electrode is exposed out of the top surface of the electrode plate, and the insulating layer covers the bottom surface of the electrode plate.
6. The package structure of claim 5, wherein the insulating layer is a solder resist ink layer.
7. The package structure of claim 6, wherein the electrode pads or interposer electrodes in the working electrode window form working electrodes by copper plating and solderable metal plating.
8. The package structure of claim 5, wherein the package structure comprises the electrode plate, the electrode plate comprises a substrate and a plurality of working electrodes embedded in the substrate holes, the working electrodes comprise top electrodes and bottom electrodes, the top surfaces of the top electrodes are exposed out of the top surfaces of the substrate, the insulating layer covers the bottom surfaces of the substrate and the bottom electrodes of the working electrodes, the substrate comprises chip transfer holes, the semiconductor devices are arranged in the chip transfer holes of the substrate, and the packaging adhesive fills the chip transfer holes and covers the semiconductor devices.
9. The package structure of claim 5, wherein the semiconductor device comprises an LED chip or diode, or a combination of an LED chip and an LED driver chip, and the LED chip comprises a Mini-LED chip or Micro-LED chip.

Description

Temporary carrier for transferring semiconductor device and packaging structure of semiconductor device [ Technical field ] The present utility model relates to miniaturized semiconductor device packages, and more particularly, to a temporary carrier for transferring semiconductor devices and a package structure of semiconductor devices. [ Background Art ] With the continuous development of semiconductor technology and the increasing demands for integration, miniaturization and high resolution of downstream applications (e.g., display and illumination), particularly the rising of Mini/Micro-LED technology, the conventional semiconductor packaging technology faces a great challenge. Conventional chip packaging methods, such as lead frame packaging (LEADFRAME PACKAGING), ball grid array packaging (BGA), flip chip bonding to a Printed Circuit Board (PCB) or ceramic substrate (COB/COG), etc., typically rely on attaching the chip to a rigid substrate by wire bonding or solder paste bonding. These methods are inefficient in handling large, small chips and have a number of problems: 1) The substrate limitation is that the traditional substrate such as PCB has the problems of low dimensional accuracy, unmatched thermal expansion Coefficient (CTE) and chip, easy warping, easy hygroscopic expansion and the like, and the problems can lead to pixel distortion, reduced connection reliability and reduced yield in high-accuracy and large-area display application. 2) The traditional wire bonding and solder paste welding process is low in speed and limited in precision, and the problems of cold joint, tin connection, soldering leakage, short circuit, wire breakage and the like are easy to occur, and particularly, the welding/wire bonding is a main yield bottleneck for a huge number of Mini/Micro-LED chips. The gold wire bonding cost is high, and the use of the aluminum electrode chip with lower cost is limited. Solder paste printing alignment accuracy is difficult to meet the requirements of Micro-LEDs. 3) The suitability of mass transfer is poor, the traditional substrate design (pad size, spacing and layout) and the subsequent connection process (welding and wire bonding) are difficult to perfectly match with the mass transfer technology required by Micro-LEDs, and the improvement of the production efficiency is limited. 4) The cost problem is that the traditional process flow is long, the material cost (such as gold wires and high-order substrates) is high, and the manufacturing cost is high. In recent years, fan-Out Packaging (Fan-Out Packaging) technology has been developed as an advanced Packaging means, wherein some forms (such as Fan-Out PANEL LEVEL PACKAGING, FOPLP) utilize temporary carriers, plastic Packaging, and forming a rewiring layer (RDL) on the surface of a plastic package body to construct a package structure, so that the limitation of wafer size is overcome, and the integration level can be improved. Mass transfer techniques have also been developed to greatly improve the transfer efficiency of microchips. However, existing FOPLP or mass transfer and packaging combined solutions remain to be optimized in terms of handling the precise alignment of extremely high density, very small size devices and ensuring the reliability of subsequent electrical connections. For example, how to provide a high-precision, easy-to-align reference for mass transfer, and how to ensure an extremely reliable connection between the micro-die pads embedded in the plastic package and the RDL layer on the surface of the plastic package, especially without using conventional soldering or wire bonding, remains a technical challenge. The invention discloses a packaging method of MIP chips, which sequentially comprises a manufacturing process of a packaging carrier plate, a huge transfer process of three-color Micro LED chips, a packaging process and a dividing process, wherein the packaging carrier plate comprises a carrier plate circuit and a glass carrier plate, the glass carrier plate is strippable and fixed on the bottom surface of the carrier plate circuit, the carrier plate circuit comprises a base plate and a plurality of unit circuits which are arranged according to an array, and each unit circuit comprises at least one group of three-color chip bonding pads, at least 4 bottom electrodes and a circuit for connecting the three-color chip bonding pads with the bottom electrodes. The invention has the following defects that 1) the electric structure of the carrier plate is complex, the universality is poor, 2) the prefabricated carrier plate circuit is likely to deform due to thermal stress when the packaging adhesive is solidified, so that the alignment of the bonding pad and the chip electrode is offset, and the alignment of the transferred semiconductor device is poor, 3) in the packaging structure, the electrode connection is mainly realized through the unit circuit of the carrier plate circuit, the unit circuit comprises a