CN-224234109-U - Display substrate and display panel

CN224234109UCN 224234109 UCN224234109 UCN 224234109UCN-224234109-U

Abstract

The embodiment of the disclosure provides a display substrate and a display panel. The display substrate comprises a display area and a non-display area which is positioned outside the display area, wherein the display substrate comprises a substrate, a plurality of thin film transistors which are positioned in the non-display area and are positioned on one side of the substrate, a first passivation layer which is positioned at least in the non-display area and is positioned on one side of the thin film transistors which are away from the substrate, a block structure which is positioned in the non-display area and is positioned on one side of the first passivation layer which is away from the substrate, the material of the block structure comprises a conductive material, and the orthographic projection of the block structure on the substrate comprises the orthographic projection of at least one thin film transistor on the substrate. When the first passivation layer is cracked, the blocky structure can cover the crack, so that the crack is protected, and poor effect caused by invasion of water vapor or other gases is avoided.

Inventors

QIAN HAIJIAO
DU RUIFANG
GUO HUI
CHENG YUANXIANG
ZHU MENGYUAN
FU YA
CHEN AISHI

Assignees

南京京东方显示技术有限公司
京东方科技集团股份有限公司

Dates

Publication Date: 20260512
Application Date: 20250430

Claims (14)

1. A display substrate comprising a display region and a non-display region located outside the display region, the display substrate comprising: A substrate; a plurality of thin film transistors located in the non-display region and on one side of the substrate; The first passivation layer is at least positioned in the non-display area and positioned at one side of the thin film transistor away from the substrate; The block structure is positioned in the non-display area and on one side of the first passivation layer, which is away from the substrate, wherein the material of the block structure comprises a conductive material, and the orthographic projection of the block structure on the substrate comprises at least one orthographic projection of the thin film transistor on the substrate.
2. The display substrate according to claim 1, wherein the thin film transistor includes a first thin film transistor, the non-display region includes a plurality of driving unit regions, the driving unit regions are provided with a shift register including a plurality of the first thin film transistors; The bulk structure comprises a first bulk pattern, the orthographic projection of the first bulk pattern onto the substrate comprising an orthographic projection of at least one of the first thin film transistors onto the substrate.
3. The display substrate according to claim 2, wherein the driving unit region is provided with a plurality of the first block patterns, and the plurality of first block patterns located in the same driving unit region are connected to each other.
4. The display substrate of claim 2, wherein the first patch pattern is located in the drive unit region, and wherein the orthographic projection of the first patch pattern on the substrate comprises the orthographic projection of the shift register on the substrate.
5. The display substrate according to claim 4, wherein each of the driving unit regions is provided with the first block pattern, and the first block patterns of adjacent driving unit regions are spaced apart from each other.
6. The display substrate according to claim 2, wherein the orthographic projection of the first patch pattern on the substrate comprises at least two adjacent drive unit regions.
7. The display substrate of claim 1, wherein the thin film transistor comprises an electrostatic shorting ring, the bulk structure comprises a second bulk pattern, and an orthographic projection of the second bulk pattern onto the substrate comprises an orthographic projection of the electrostatic shorting ring onto the substrate.
8. The display substrate according to claim 1, further comprising a first metal layer, a first insulating layer, and a second metal layer sequentially disposed between the substrate and the first passivation layer, the display substrate comprising a first metal pattern on the first metal layer and a second metal pattern on the second metal layer, the first insulating layer being provided with a first via hole on the non-display region, the second metal pattern being coupled with the first metal pattern through the first via hole; the orthographic projection of the block structure on the substrate further includes an orthographic projection of the first via on the substrate.
9. The display substrate of any one of claims 1-8, further comprising a first transparent conductive layer on a side of the first passivation layer facing away from the substrate, the bulk structure comprising a first conductive bump on the first transparent conductive layer.
10. The display substrate of claim 9, further comprising a second passivation layer and a second transparent conductive layer, the second passivation layer being on a side of the first transparent conductive layer facing away from the substrate, the second transparent conductive layer being on a side of the second passivation layer facing away from the substrate, the bulk structure further comprising a second conductive block on the second transparent conductive layer.
11. The display substrate of claim 9, further comprising a third metal layer on a side of the first transparent conductive layer facing away from the substrate, the bulk structure further comprising a third conductive bump on the third metal layer.
12. The display substrate according to any one of claims 1 to 7, wherein the display substrate comprises a first metal layer, a first insulating layer, a second metal layer, the first passivation layer, a first transparent conductive layer, a second passivation layer, and a second transparent conductive layer, which are sequentially stacked, and the bulk structure comprises a first conductive block located in the first transparent conductive layer; The first metal layer comprises a first metal pattern positioned in the non-display area, the second metal layer comprises a second metal pattern positioned in the non-display area, and the second transparent conductive layer comprises a patch cord positioned in the non-display area; The first conductive block is provided with a hollowed-out portion, the non-display area is provided with a second via hole and a third via hole, the second via hole penetrates through the second passivation layer, the first passivation layer and the first insulation layer, the orthographic projection of the second via hole on the substrate is located in the orthographic projection of the hollowed-out portion on the substrate, the third via hole penetrates through the second passivation layer and the first passivation layer, the orthographic projection of the third via hole on the substrate is located in the orthographic projection of the hollowed-out portion on the substrate, and the patch cord is coupled with the first metal pattern through the second via hole and is coupled with the second metal pattern through the third via hole.
13. The display substrate according to any one of claims 1 to 8, wherein, The display substrate further comprises a common electrode line in the non-display region, the block structure is coupled with the common electrode line, or The display substrate further includes a common ground trace in the non-display region, and the block structure is coupled with the common ground trace.
14. A display panel comprising the display substrate of any one of claims 1-13.

Description

Display substrate and display panel Technical Field The disclosure relates to the field of display technologies, and in particular, to a display substrate and a display panel. Background In the technical field of display, a substrate is formed by accumulating a layer of film layers, an insulating layer is usually arranged between two adjacent metal layers, and a passivation layer is arranged above the metal layers for protecting the substrate so as to prevent water vapor from invading the substrate. In the related art, there is a problem in that moisture or other gas intrudes into the inside of the substrate, causing defective products. Disclosure of utility model Embodiments of the present disclosure provide a display substrate and a display panel to solve or alleviate one or more technical problems in the prior art. As a first aspect of the embodiments of the present disclosure, the embodiments of the present disclosure provide a display substrate including a display region and a non-display region located outside the display region, the display substrate including: A substrate; a plurality of thin film transistors located in the non-display region and on one side of the substrate; The first passivation layer is at least positioned in the non-display area and positioned at one side of the thin film transistor, which is away from the substrate; The block structure is positioned in the non-display area and on one side of the first passivation layer, which is away from the substrate, the material of the block structure comprises a conductive material, and the orthographic projection of the block structure on the substrate comprises the orthographic projection of at least one thin film transistor on the substrate. In some embodiments, the thin film transistor includes a first thin film transistor, the non-display region includes a plurality of driving unit regions, the driving unit regions are provided with a shift register, and the shift register includes a plurality of first thin film transistors; The bulk structure comprises a first bulk pattern, the orthographic projection of the first bulk pattern onto the substrate comprising an orthographic projection of at least one first thin film transistor onto the substrate. In some embodiments, the driving unit region is provided with a plurality of first block patterns, and the plurality of first block patterns located in the same driving unit region are connected to each other. In some embodiments, the first patch pattern is located in the drive unit region, and the orthographic projection of the first patch pattern on the substrate includes an orthographic projection of the shift register on the substrate. In some embodiments, each driving unit region is provided with a first block pattern, and the first block patterns of adjacent driving unit regions are spaced apart from each other. In some embodiments, the orthographic projection of the first patch pattern on the substrate includes at least two drive unit regions adjacent to each other. In some embodiments, the thin film transistor includes an electrostatic shorting ring, the bulk structure includes a second bulk pattern, and an orthographic projection of the second bulk pattern onto the substrate includes an orthographic projection of the electrostatic shorting ring onto the substrate. In some embodiments, the display substrate further includes a first metal layer, a first insulating layer, and a second metal layer sequentially disposed between the substrate and the first passivation layer, the display substrate includes a first metal pattern located on the first metal layer, and a second metal pattern located on the second metal layer, the first insulating layer is provided with a first via hole located in the non-display region, and the second metal pattern is coupled with the first metal pattern through the first via hole; The orthographic projection of the bulk structure onto the substrate further includes an orthographic projection of the first via onto the substrate. In some embodiments, the first passivation layer is disposed on a side of the first passivation layer facing away from the substrate, and the bulk structure includes a first conductive bump disposed on the first transparent conductive layer. In some embodiments, the display substrate further comprises a second passivation layer and a second transparent conductive layer, the second passivation layer being located on a side of the first transparent conductive layer facing away from the substrate, the second transparent conductive layer being located on a side of the second passivation layer facing away from the substrate, the bulk structure further comprising a second conductive bump located on the second transparent conductive layer. In some embodiments, a third metal layer is further included, the third metal layer being located on a side of the first transparent conductive layer facing away from the substrate, the bulk structure further