CN-224234111-U - Display panel

CN224234111UCN 224234111 UCN224234111 UCN 224234111UCN-224234111-U

Abstract

The application relates to a display panel, which comprises a display area, a non-display area adjacent to the display area, a pixel definition layer and a printing layer, wherein a plurality of first openings positioned in the display area and a second opening at least positioned in the pixel definition layer and positioned in the non-display area are formed in the pixel definition layer, the printing layer comprises a plurality of pixel printing parts arranged in the plurality of first openings, wherein the depth of the second opening in the thickness direction of the display panel is larger than the thickness of the pixel definition layer.

Inventors

LIU JIANXIN
Request for anonymity
HAN BAIXIANG

Assignees

武汉华星光电技术有限公司

Dates

Publication Date: 20260512
Application Date: 20250509

Claims (10)

1. A display panel, wherein the display panel includes a display area and a non-display area adjacent to the display area, the display panel further comprising: A pixel defining layer having a plurality of first openings formed therein within the display region, and a second opening formed at least in the pixel defining layer and within the non-display region; A print layer including a plurality of pixel print sections provided in a plurality of the first openings; Wherein the depth of the second opening in the thickness direction of the display panel is greater than the thickness of the pixel defining layer.
2. The display panel according to claim 1, the display panel is characterized in that the display panel further comprises: the pixel definition layer is arranged on one side of the substrate; an array layer disposed between the substrate and the pixel definition layer; the distance between the bottom surface of the second opening and the substrate is smaller than the thickness of the array layer.
3. The display panel of claim 2, wherein the array layer comprises: A first conductive layer disposed between the substrate and the pixel defining layer; A first planarization layer disposed between the first conductive layer and the pixel definition layer; a second flat layer disposed between the first flat layer and the first conductive layer; the distance between the bottom surface of the second opening and the substrate is smaller than the distance between one surface of the first flat layer, which is far away from the substrate, and the substrate.
4. The display panel of claim 3, wherein the second opening passes through the pixel defining layer and the first planarization layer; or a third opening is formed in the second flat layer, the first flat layer covers the side wall and the bottom surface of the third opening, and the third opening is located between the second opening and the substrate.
5. A display panel according to claim 3, wherein the array layer comprises: A second conductive layer disposed between the substrate and the first conductive layer; A third flat layer disposed between the second conductive layer and the first conductive layer; an insulating layer disposed between the third planarization layer and the second conductive layer; wherein at least one of the third planarization layer and the insulating layer is formed with a fourth opening between the second opening and the substrate.
6. The display panel according to claim 5, wherein the first conductive layer includes a first signal line disposed in the non-display region, the first signal line includes a first line segment and a second line segment connected to each other, the first line segment is disposed corresponding to the fourth opening, and a distance between the first line segment and the substrate is smaller than a distance between the second line segment and the substrate.
7. The display panel of claim 5, wherein a third opening is formed in the second flat layer, the fourth opening is formed in the third flat layer, the third opening is in communication with the fourth opening, and both the third opening and the fourth opening are located between the second opening and the substrate; wherein the first flat layer covers the side wall of the third opening, the side wall of the fourth opening and the bottom surface of the fourth opening.
8. The display panel according to claim 5, wherein a third opening is formed in the second flat layer, wherein the fourth opening is formed in the insulating layer, wherein the third opening is located between the second opening and the fourth opening, and wherein the fourth opening is located between the third opening and the substrate; The first flat layer covers the side wall and the bottom surface of the third opening, and the third flat layer covers the side wall and the bottom surface of the fourth opening.
9. The display panel of any one of claims 1 to 8, wherein the print layer further comprises a virtual print disposed within the non-display region, the virtual print being located within the second opening.
10. The display panel of claim 9, wherein the display panel further comprises: The anode layer comprises a plurality of first anodes arranged in the display area and a plurality of second anodes arranged in the non-display area, the first anodes are arranged corresponding to the pixel printing portions, the pixel printing portions are located at one sides of the corresponding first anodes, which are close to the light emitting surface of the display panel, and the virtual printing portions are located at one sides of the second anodes, which are close to the light emitting surface of the display panel.

Description

Display panel Technical Field The application relates to the technical field of display, in particular to a display panel. Background An Organic Light-Emitting Diode (OLED) has advantages of self-luminescence, fast response, wide viewing angle, high brightness, bright color, light and thin, etc., and is considered as a next generation display technology. The thin film deposition method of the organic light-emitting diode (OLED) mainly comprises two processes of vacuum evaporation and solution process. In the inkjet printing process, the drying rate of the solvent in the edge area of the inkjet printing is faster than that in the display area, and in order to ensure uniformity of the film formation between pixels and uniformity of the brightness of the corresponding device, it is generally necessary to provide auxiliary pixels in the edge area, that is, to print ink also in the auxiliary pixels, but the auxiliary pixels do not emit light when the device is lit. In order to meet the above design requirement, a plurality of auxiliary pixels are usually required to be disposed in the edge area to accommodate more ink so as to make the film forming uniform, but this also makes the occupied area of the frame corresponding to the edge area larger, which is not beneficial to the design requirement of the narrow frame. Disclosure of utility model The embodiment of the application provides a display panel, which can increase the capacity of ink in a second opening, thereby being beneficial to improving the film forming uniformity of a pixel printing part and being beneficial to narrowing the frame of the display panel. An embodiment of the present application provides a display panel, where the display panel includes a display area and a non-display area adjacent to the display area, and the display panel further includes: A pixel defining layer having a plurality of first openings formed therein within the display region, and a second opening formed at least in the pixel defining layer and within the non-display region; A print layer including a plurality of pixel print sections provided in a plurality of the first openings; Wherein the depth of the second opening in the thickness direction of the display panel is greater than the thickness of the pixel defining layer. In one embodiment of the present application, the display panel further includes: the pixel definition layer is arranged on one side of the substrate; an array layer disposed between the substrate and the pixel definition layer; the distance between the bottom surface of the second opening and the substrate is smaller than the thickness of the array layer. In one embodiment of the application, the array layer comprises: A first conductive layer disposed between the substrate and the pixel defining layer; A first planarization layer disposed between the first conductive layer and the pixel definition layer; a second flat layer disposed between the first flat layer and the first conductive layer; the distance between the bottom surface of the second opening and the substrate is smaller than the distance between one surface of the first flat layer, which is far away from the substrate, and the substrate. In one embodiment of the application, the second opening passes through the pixel defining layer and the first planarization layer; or a third opening is formed in the second flat layer, the first flat layer covers the side wall and the bottom surface of the third opening, and the third opening is located between the second opening and the substrate. In one embodiment of the application, the array layer comprises: A second conductive layer disposed between the substrate and the first conductive layer; A third flat layer disposed between the second conductive layer and the first conductive layer; an insulating layer disposed between the third planarization layer and the second conductive layer; wherein at least one of the third planarization layer and the insulating layer is formed with a fourth opening between the second opening and the substrate. In an embodiment of the application, the first conductive layer includes a first signal line disposed in the non-display area, the first signal line includes a first line segment and a second line segment that are connected, the first line segment is disposed corresponding to the fourth opening, and a distance between the first line segment and the substrate is smaller than a distance between the second line segment and the substrate. In one embodiment of the present application, a third opening is formed in the second flat layer, the fourth opening is formed in the third flat layer, the third opening is in communication with the fourth opening, and both the third opening and the fourth opening are located between the second opening and the substrate; wherein the first flat layer covers the side wall of the third opening, the side wall of the fourth opening and the bottom surface of the fourth opening. In one e