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CN-224234195-U - Semiconductor device with a semiconductor layer having a plurality of semiconductor layers

CN224234195UCN 224234195 UCN224234195 UCN 224234195UCN-224234195-U

Abstract

The application relates to a semiconductor device, wherein an insulating layer is formed by adopting a ceramic material, a chip comprises a first chip and a second chip, a pin comprises a first pin, a second pin and a third pin, a first metal layer is adhered to the first surface of the insulating layer, the first metal layer comprises a first base island, a second base island and a third base island which are mutually isolated, the first chip and the second chip are mutually isolated and mounted on the second base island, the first chip and the second chip are electrically connected through a bonding wire, the first chip is electrically connected with the first base island, the second chip is electrically connected with the third base island, and the first pin, the second pin and the third pin are sequentially welded on the first base island, the second base island and the third base island. The semiconductor device can solve the problems that the prior semiconductor device needs to be additionally provided with an insulating heat conducting sheet when being assembled with a radiator, so that on one hand, the assembly complexity is increased, and on the other hand, layering easily occurs, and the resistance performance of the semiconductor device is reduced along with the increase of the service life.

Inventors

  • LI SONGYANG
  • LEI MING
  • ZHU DONGYING

Assignees

  • 珠海格力电子元器件有限公司

Dates

Publication Date
20260512
Application Date
20250526

Claims (10)

  1. 1. The semiconductor device is characterized by comprising a first metal layer (1), an insulating layer (3), a chip and a plurality of pins, wherein the insulating layer (3) is formed by adopting a ceramic material, the chip comprises a first chip (41) and a second chip (42), the pins comprise a first pin (51), a second pin (52) and a third pin (53), the first metal layer (1) is attached to the first surface of the insulating layer (3), the first metal layer (1) comprises a first base island (11), a second base island (12) and a third base island (13) which are isolated from each other, the first chip (41) and the second chip (42) are installed on the second base island (12) in an isolated manner, the first chip (41) and the second chip (42) are electrically connected through bonding wires (6), the first chip (41) is electrically connected with the first base island (11), and the second chip (42) is electrically connected with the third base island (13), the first base island (51) and the third pin (53) are sequentially welded with the second base island (13).
  2. 2. The semiconductor device according to claim 1, further comprising a second metal layer (2), wherein the second metal layer (2) is attached to a second surface of the insulating layer (3), the second surface is opposite to the first surface, and a side surface of the second metal layer (2) facing away from the insulating layer (3) is in thermal connection with a heat sink.
  3. 3. The semiconductor device according to claim 2, characterized in that the first metal layer (1) and the second metal layer (2) are each formed of metallic copper.
  4. 4. A semiconductor device according to claim 2, characterized in that the surface roughness of the side of the second metal layer (2) facing away from the insulating layer (3) is less than or equal to 2 μm.
  5. 5. The semiconductor device according to claim 1, wherein an outer edge of at least one of the first base island (11), the second base island (12), and the third base island (13) is provided with a chamfer.
  6. 6. The semiconductor device according to claim 1, wherein a side surface of the first metal layer (1) facing the insulating layer (3) has a roughened structure.
  7. 7. The semiconductor device according to claim 1, characterized in that the semiconductor device comprises an insulating housing (7), the first metal layer (1), the insulating layer (3) and the chip are all mounted in the insulating housing (7), the insulating housing (7) is provided with a groove (71) and a plurality of through holes, a plurality of pins extend out of the insulating housing (7) from the plurality of through holes in a one-to-one correspondence, and the grooves (71) are all arranged between adjacent pins.
  8. 8. A semiconductor device according to claim 7, characterized in that the insulating housing (7) is formed using thermosetting plastic and alumina particles.
  9. 9. The semiconductor device according to claim 7, wherein an outer edge of the insulating layer is located outside an outer edge of the first metal layer in a direction perpendicular to a thickness direction of the insulating layer.
  10. 10. A semiconductor device according to claim 9, characterized in that the projected area of the insulating layer (3) is less than or equal to two-thirds of the projected area of the insulating housing (7) in a plane perpendicular to the thickness direction of the insulating layer (3).

Description

Semiconductor device with a semiconductor layer having a plurality of semiconductor layers Technical Field The present application relates to the field of semiconductors, and more particularly, to a semiconductor device. Background TO package structures are common semiconductor devices that typically include a leadframe and a chip mounted on the leadframe, and a heat spreader is typically disposed on the backside of the leadframe in order TO increase the heat dissipation efficiency of the chip. However, in the current semiconductor device, when the heat sink is mounted, an insulating heat conducting sheet needs to be arranged between the lead frame and the heat sink, so that on one hand, the assembly complexity is increased, and on the other hand, due to different materials on two opposite sides of the frame, layering easily occurs between the frame and the insulating heat conducting sheet, and the pressure resistance is reduced along with the increase of the service time. Disclosure of utility model The application provides a semiconductor device, which aims to solve the problems that when a radiator is assembled in the traditional semiconductor device, an insulating heat conducting sheet is required to be additionally arranged, so that on one hand, the assembly complexity is increased, and on the other hand, layering easily occurs, and the resistance performance of the semiconductor device is reduced along with the increase of the service time. The application provides a semiconductor device, which comprises a first metal layer, an insulating layer, a chip and a plurality of pins, wherein the insulating layer is formed by adopting a ceramic material, the chip comprises a first chip and a second chip, the pins comprise a first pin, a second pin and a third pin, the first metal layer is adhered to the first surface of the insulating layer, the first metal layer comprises a first base island, a second base island and a third base island which are mutually isolated, the first chip and the second chip are mutually isolated and are arranged on the second base island, the first chip and the second chip are electrically connected through bonding wires, the first chip is electrically connected with the first base island, the second chip is electrically connected with the third base island, and the first pin, the second pin and the third pin are sequentially welded on the first base island, the second base island and the third base island. The embodiment of the application provides a semiconductor device, wherein an insulating layer is formed by adopting a ceramic material, so that the thermal expansion coefficients between the insulating layers respectively positioned at two opposite sides of a first metal layer and a chip are equivalent, meanwhile, in the embodiment of the application, the insulating layer can be utilized to realize the purpose of internal insulation of the device, so that the chip arranged at one side of the first metal layer, which is far away from the insulating layer, can form a good electrical insulation relationship with the outside, and the side of the insulating layer, which is far away from the first metal layer, can be directly in heat conduction connection with a radiator, thus an insulating heat conducting sheet and a heat conducting silicone coating are not required to be added in the installation process, the installation process is simplified, and the assembly time can be reduced by 35%. Moreover, under the condition of adopting the technical scheme of the application, the heat dissipation path is shortened, and the insulating layer made of ceramic material can provide relatively higher reliability and relatively lower thermal resistance for the chip, wherein the voltage withstand performance of the insulating layer can reach 2500V AC r.m.s, the voltage withstand level of the insulating layer is more than 3.5kV, the partial discharge initial voltage can be raised to more than 2.2kV, and the requirements of high-voltage scenes such as a photovoltaic inverter, an electric automobile and the like are met. In addition, under the condition that the technical scheme disclosed by the embodiment of the application is adopted, the first chip and the second chip are mutually arranged on the second base island of the first metal layer in an isolated manner and are electrically connected through the bonding wire, meanwhile, the first chip is also electrically connected with the first base island, the second chip is also electrically connected with the third base island, in the condition, the first pin, the second pin and the third pin can be directly and sequentially welded on the first base island, the second base island and the third base island, so that the installation complexity of a plurality of pins is reduced, and under the condition that the technical scheme is adopted, the length of each current loop of the first chip and the second chip is also shortened, stray inductance is reduced