CN-224234201-U - Semiconductor package and semiconductor package module

Abstract

The semiconductor package may include a first lead frame, an element outputting a signal corresponding to a current flowing through the first lead frame, a second lead frame electrically insulated from the first lead frame and outputting a signal corresponding to the signal from the element, and a sealing portion sealing the element, a portion of the first lead frame, and a portion of the second lead frame with resin. The terminal portion of the first lead frame may be exposed from the first face of the sealing portion. The terminal portion of the second lead frame may be exposed from a second face of the sealing portion opposite to the first face in the first direction. The seal portion may have at least one groove extending in a second direction intersecting the first direction on at least one surface other than the first surface and the second surface.

Inventors

• TSUKIHARA HISATO

Assignees

• 旭化成微电子株式会社

Dates

Publication Date

20260512

Application Date

20240219

Priority Date

20230220

Claims (20)

1. 1. A semiconductor package is characterized in that, The semiconductor package includes: A first lead frame; An element outputting a signal corresponding to a current flowing through the first lead frame; A second lead frame electrically insulated from the first lead frame and outputting a signal corresponding to the signal from the element, and A sealing part for sealing the element, a part of the first lead frame and a part of the second lead frame with a resin, The terminal portion of the first lead frame is exposed from the first face of the sealing portion, The terminal portion of the second lead frame is exposed from a second face of the sealing portion opposite to the first face in the first direction, The seal portion has at least one groove extending in a second direction intersecting the first direction on at least one surface other than the first surface and the second surface.
2. 2. The semiconductor package according to claim 1, wherein, The sealing portion includes third and fourth faces opposed to each other in a thickness direction, and fifth and sixth faces opposed to each other in the second direction intersecting the first direction and the thickness direction respectively, The at least one slot includes a first slot extending from the fifth face toward the sixth face at the third face and the fourth face, respectively.
3. 3. The semiconductor package according to claim 2, wherein, The first slot extends along the second direction.
4. 4. The semiconductor package according to claim 2, wherein, The at least one slot includes a second slot extending from the third face toward the fourth face at the fifth face and the sixth face, respectively.
5. 5. The semiconductor package according to claim 4, wherein, The second groove extends in the thickness direction.
6. 6. The semiconductor package according to claim 4, wherein, The first slot communicates with the second slot.
7. 7. The semiconductor package according to claim 1, wherein, The sealing portion includes third and fourth faces opposed to each other in a thickness direction, and fifth and sixth faces opposed to each other in the second direction intersecting the first direction and the thickness direction respectively, The at least one groove includes grooves along the third face, the fourth face, the fifth face, and the sixth face for one consecutive revolution.
8. 8. The semiconductor package according to claim 1, wherein, The recess width of the at least one groove is 1mm or more.
9. 9. The semiconductor package according to claim 1, wherein, The at least one groove has a depth of 0.5mm or more.
10. 10. The semiconductor package according to claim 1, wherein, The seal portion includes a plurality of grooves as the at least one groove, and at least one groove of the plurality of grooves is spaced apart more widely than other grooves than the at least one groove of the plurality of grooves.
11. 11. The semiconductor package according to claim 1, wherein, The seal portion includes a plurality of grooves as the at least one groove, and a space between grooves of a central portion in the first direction of the plurality of grooves is wider than a space between grooves other than the grooves of the central portion.
12. 12. The semiconductor package according to claim 1, wherein, The terminal portion of the first lead frame is electrically connected to a first power supply system, and the terminal portion of the second lead frame is connected to a second power supply system to which a voltage lower than the first power supply system is applied.
13. 13. The semiconductor package according to claim 2, wherein, The arrangement surface of each of the terminal portion of the first lead frame and the terminal portion of the second lead frame is located outside the thickness direction with respect to the third surface or fourth surface when viewed from the second direction.
14. 14. The semiconductor package according to claim 1, wherein, The side surface of the at least one groove is inclined so as to expand as seen from the bottom surface toward the opening when viewed from the second direction.
15. 15. The semiconductor package according to claim 14, wherein, The side surface of the at least one groove has an inclination angle of 85 degrees or less with respect to the bottom surface.
16. 16. The semiconductor package according to claim 1, wherein, The convex side of the at least one groove is chamfered or rounded by 0.1mm or more.
17. 17. The semiconductor package according to claim 1, wherein, The sealing portion seals the element, a portion of the first lead frame, and a portion of the second lead frame with a molding resin.
18. 18. The semiconductor package according to claim 1, wherein, The element is at least one magneto-electric conversion element that outputs a signal corresponding to a magnitude of a magnetic field generated by a current flowing through the first lead frame.
19. 19. The semiconductor package according to claim 16, wherein, The semiconductor package further includes a signal processing IC that processes the signal output from the at least one magneto-electric conversion element and outputs the processed signal via the second lead frame, The sealing portion also seals the signal processing IC.
20. 20. The semiconductor package according to claim 19, wherein, The at least one magneto-electric converting element is electrically connected with the signal processing IC via a first wire, The signal processing IC is electrically connected to the second leadframe via a second wire, The at least one groove is provided at a position not overlapping the first wire and the second wire in a plan view.

Description

Semiconductor package and semiconductor package module Technical Field The present utility model relates to a semiconductor package. Background Patent document 1 discloses a current sensor including a conductor having a lead terminal through which a current to be measured flows, a magneto-electric conversion element outputting a signal having a magnitude proportional to a magnetic field generated by the current flowing through the conductor, a signal processing IC processing the signal, and other lead terminals outputting a signal from the signal processing IC, wherein the current sensor is a semiconductor package in which the conductor, the magneto-electric conversion element, and the signal processing IC are sealed with a molded resin. Prior art literature Patent literature Patent document 1 Japanese patent No. 6321800 Disclosure of utility model Problems to be solved In the semiconductor package as described above, it is desirable to secure insulation between lead terminals while suppressing an increase in size of the package even when used at a high operating voltage. General disclosure The semiconductor package according to one embodiment of the present utility model may include a first lead frame, an element that outputs a signal corresponding to a current flowing through the first lead frame, a second lead frame that is electrically insulated from the first lead frame and outputs a signal corresponding to the signal from the element, and a sealing portion that seals the element, a part of the first lead frame, and a part of the second lead frame with resin. The terminal portion of the first lead frame may be exposed from the first face of the sealing portion. The terminal portion of the second lead frame may be exposed from a second face of the sealing portion opposite to the first face in the first direction. The seal portion may have at least one groove extending in a second direction intersecting the first direction on at least one surface other than the first surface and the second surface. In the semiconductor package, the sealing portion may include a third face and a fourth face opposite to each other in a thickness direction, and a fifth face and a sixth face opposite to each other in the second direction intersecting the first direction and the thickness direction, respectively. The at least one groove may include a first groove extending from the fifth surface toward the sixth surface at the third surface and the fourth surface, respectively. In any of the semiconductor packages, the first groove may extend along the second direction. In any of the semiconductor packages, the at least one groove may include a second groove extending from the third face toward the fourth face at the fifth face and the sixth face, respectively. In any of the semiconductor packages, the second groove may extend in the thickness direction. In any of the semiconductor packages, the first groove may communicate with the second groove. In any of the semiconductor packages, the sealing portion may include a third face and a fourth face that are opposite to each other in a thickness direction, and a fifth face and a sixth face that are opposite to each other in the second direction that respectively intersect the first direction and the thickness direction. The at least one groove may include grooves continuous one week along the third face, the fourth face, the fifth face, and the sixth face. In any of the above semiconductor packages, the recess width of the at least one groove may be 1mm or more. In any of the above semiconductor packages, the at least one groove may have a depth of 0.5mm or more. In any of the semiconductor packages, the sealing portion may include a plurality of grooves as the at least one groove, and at least one groove of the plurality of grooves may be spaced apart more than other grooves than the at least one groove of the plurality of grooves. In any of the semiconductor packages, the sealing portion may include a plurality of grooves as the at least one groove, and a space between grooves in a central portion in the first direction of the plurality of grooves may be wider than a space between grooves other than the grooves in the central portion. In any of the semiconductor packages, the terminal portion of the first lead frame may be electrically connected to a first power supply system, and the terminal portion of the second lead frame may be connected to a second power supply system to which a voltage lower than the first power supply system is applied. In the semiconductor package, the terminal portion of the first lead frame and the terminal portion of the second lead frame may be arranged such that a surface of the terminal portion of the first lead frame is located outside the third surface or the fourth surface in the thickness direction when viewed from the second direction. In any of the semiconductor packages, the side surface of the at least one groove may be inclined so as to