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CN-224234202-U - Semiconductor packaging structure

CN224234202UCN 224234202 UCN224234202 UCN 224234202UCN-224234202-U

Abstract

The utility model discloses a semiconductor packaging structure which comprises a lead frame, a first MOS chip and a second MOS chip, wherein a first electrode is arranged on the front surface of the first MOS chip, a second electrode and a third electrode are arranged on the back surface of the first MOS chip, the first MOS chip is arranged on a base island and is electrically connected with the base island, a fourth electrode is arranged on the front surface of the second MOS chip, a fifth electrode and a sixth electrode are arranged on the back surface of the first MOS chip, the second MOS chip is stacked on the first MOS chip, the fourth electrode is electrically connected with the second electrode, a first connecting pin is electrically connected with the sixth electrode of the second MOS chip, the second connecting pin is respectively electrically connected with the third electrode of the first MOS chip and the fifth electrode of the second MOS chip, and the first MOS chip and the second MOS chip which are connected in series are packaged in an up-down stacking mode, so that the occupied area of the first MOS chip and the second MOS chip in the semiconductor packaging structure is effectively reduced, and the packaging of multiple MOS chips is facilitated.

Inventors

  • YAN WEIJING

Assignees

  • 聚源创富(深圳)半导体有限公司

Dates

Publication Date
20260512
Application Date
20250430

Claims (10)

  1. 1. The semiconductor packaging structure is characterized by comprising a lead frame, a first MOS chip and a second MOS chip; The lead frame comprises a base island, and a first connecting pin, a second connecting pin and a third connecting pin which are arranged on the periphery of the base island, wherein the third connecting pin is electrically connected with the base island; The front surface of the first MOS chip is provided with a first electrode, and the back surface of the first MOS chip is provided with a second electrode and a third electrode; A fourth electrode is arranged on the front surface of the second MOS chip, and a fifth electrode and a sixth electrode are arranged on the back surface of the first MOS chip; the second MOS chip is stacked on the first MOS chip, and the fourth electrode is electrically connected with the second electrode; the first connecting pin is electrically connected with the sixth electrode of the second MOS chip, and the second connecting pin is electrically connected with the third electrode of the first MOS chip and the fifth electrode of the second MOS chip respectively.
  2. 2. The semiconductor package according to claim 1, wherein the semiconductor package comprises an electrical connection and an insulating support; The electric connecting piece comprises a connecting body, a first connecting part and a second connecting part, wherein the first connecting part and the second connecting part extend along two sides of the length direction of the connecting body; The second MOS chip is arranged on the electric connecting piece, and the fourth electrode of the second MOS chip is electrically connected with the second electrode of the first MOS chip through the electric connecting piece.
  3. 3. The semiconductor package according to claim 2, wherein the first connection portion covers a partial region of the back surface of the first MOS chip, other regions of the back surface of the first MOS chip form an exposed region, and the third electrode of the first MOS chip is disposed in the exposed region.
  4. 4. The semiconductor package according to claim 3, wherein the first connection portion has an L-shape.
  5. 5. The semiconductor package according to claim 2, wherein the first region of the first connection portion forms a first deformation portion protruding to one side by a stamping process, the first deformation portion including a first inclined sidewall and a first top land smoothly transiting with the connection body; A first continuous plane area which is not punched is arranged around the first deformation part, and the thickness of the first continuous plane area is the same as that of the connecting body; The first top land is at least partially electrically connected to the second electrode of the first MOS chip.
  6. 6. The semiconductor package according to claim 2, wherein the second region of the second connection portion forms a second deformation portion protruding to one side by a stamping process, the second deformation portion including a second inclined sidewall and a second top land smoothly transiting with the connection body; a second continuous plane area which is not punched is arranged around the second deformation part, and the thickness of the second continuous plane area is the same as that of the connecting body; one end of the insulating support piece is fixedly connected with the second top platform, and the other end of the insulating support piece is fixedly connected with the base island.
  7. 7. The semiconductor package according to claim 2, wherein the electrical connector is copper.
  8. 8. The semiconductor package according to claim 2, wherein the insulating support member is made of a high-temperature resistant insulating material.
  9. 9. The semiconductor package according to claim 1, wherein the sixth electrode of the second MOS chip is electrically connected to the first connection pin through a first wire; The third electrode of the first MOS chip is electrically connected with the second connecting pin through a second wire, and the fifth electrode of the second MOS chip is electrically connected with the second connecting pin through a third wire.
  10. 10. The semiconductor package according to claim 1, wherein the lead frame further comprises a fourth connection pin electrically connected to the first connection pin, the fourth connection pin being disposed adjacent to the first connection pin, the fourth connection pin being electrically connected to a sixth electrode of the second MOS chip through a fourth wire.

Description

Semiconductor packaging structure Technical Field The present disclosure relates to semiconductor technology, and more particularly, to a semiconductor package structure. Background With the continuous development of the semiconductor industry and the continuous miniaturization and weight reduction of consumer electronic products such as smart phones, tablet computers and wearable devices, the demand for high-performance and small-size power semiconductor devices is increasing, and many times, multiple semiconductor devices are required to be combined for use. As an important semiconductor device in these devices, the demand of the market for miniaturized MOS packages is also increasing, and smart products are more required to be light, thin, short and small compared with the application of the electronic products of the previous generation, especially in the field of portable electronic products, and the wearable headset or the wrist-watch, and the like, and have higher requirements on the occupied area and thickness of parts. At present, a tiling mode is mostly adopted in the prior art for packaging the multiple MOS tubes, and when the packaging structure is adopted for packaging the multiple MOS tubes, the space occupation is large due to the fact that each MOS tube adopts the tiling mode, so that the requirement of miniaturized semiconductor packaging is not met. Disclosure of utility model The embodiment of the utility model provides a semiconductor packaging structure, which aims to solve the problem that the existing semiconductor packaging structure is large in size. A semiconductor package structure includes a lead frame, a first MOS chip, and a second MOS chip; The lead frame comprises a base island, and a first connecting pin, a second connecting pin and a third connecting pin which are arranged on the periphery of the base island, wherein the third connecting pin is electrically connected with the base island; The front surface of the first MOS chip is provided with a first electrode, and the back surface of the first MOS chip is provided with a second electrode and a third electrode; A fourth electrode is arranged on the front surface of the second MOS chip, and a fifth electrode and a sixth electrode are arranged on the back surface of the first MOS chip; the second MOS chip is stacked on the first MOS chip, and the fourth electrode is electrically connected with the second electrode; the first connecting pin is electrically connected with the sixth electrode of the second MOS chip, and the second connecting pin is electrically connected with the third electrode of the first MOS chip and the fifth electrode of the second MOS chip respectively. Further, the semiconductor package structure includes an electrical connection and an insulating support; The electric connecting piece comprises a connecting body, a first connecting part and a second connecting part, wherein the first connecting part and the second connecting part extend along two sides of the length direction of the connecting body; The second MOS chip is arranged on the electric connecting piece, and the fourth electrode of the second MOS chip is electrically connected with the second electrode of the first MOS chip through the electric connecting piece. Further, the first connection portion covers a part of the area on the back of the first MOS chip, an exposed area is formed in other areas on the back of the first MOS chip, and the third electrode of the first MOS chip is disposed in the exposed area. Further, the first connecting portion is L-shaped. Further, a first deformation part protruding to one side is formed in a first area of the first connecting part through a stamping process, and the first deformation part comprises a first inclined side wall and a first top platform which are in smooth transition with the connecting body; A first continuous plane area which is not punched is arranged around the first deformation part, and the thickness of the first continuous plane area is the same as that of the connecting body; The first top land is at least partially electrically connected to the second electrode of the first MOS chip. Further, a second deformation part protruding to one side is formed in a second area of the second connecting part through a stamping process, and the second deformation part comprises a second inclined side wall and a second top platform which are in smooth transition with the connecting body; a second continuous plane area which is not punched is arranged around the second deformation part, and the thickness of the second continuous plane area is the same as that of the connecting body; one end of the insulating support piece is fixedly connected with the second top platform, and the other end of the insulating support piece is fixedly connected with the base island. Further, the electrical connector is made of copper. Further, the insulating support piece is made of high-temperature resistant insu