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DE-102012025859-B4 - ELECTRONIC COMPONENT AND COATED SEMICONDUCER SUBSTRATE

DE102012025859B4DE 102012025859 B4DE102012025859 B4DE 102012025859B4DE-102012025859-B4

Abstract

Coated semiconductor substrate (2,3), comprising: a semiconductor substrate (2); and a layer system (3) arranged on the semiconductor substrate (2); wherein the layer system (3) comprises: an electrical contact layer (3.1) which is arranged directly on the semiconductor substrate (2), wherein the electrical contact layer (3.1) is a single-element layer of Al; a functional layer (3.2) arranged directly on the electrical contact layer (3.1), wherein the functional layer (3.2) comprises Ti or an alloy comprising Ti; an adhesive layer (3.3) which is arranged directly on the functional layer (3.2), wherein the adhesive layer (3.3) comprises Ni; a solder layer (3.4) which is arranged directly on the adhesive layer (3.3), wherein the solder layer (3.4) is a single-element layer of Sn; a protective layer (43.5) that is arranged directly on the solder layer (3.4).

Inventors

  • Michael Juerss
  • Konrad Roesl
  • Oliver EICHINGER
  • Kok Chai Goh
  • Tobias Schmidt
  • Alexander Heinrich

Assignees

  • INFINEON TECHNOLOGIES AG

Dates

Publication Date
20260513
Application Date
20121130
Priority Date
20111201

Claims (18)

  1. Coated semiconductor substrate (2, 3) comprising: a semiconductor substrate (2); and a layer system (3) arranged on the semiconductor substrate (2); wherein the layer system (3) comprises: an electrical contact layer (3.1) arranged directly on the semiconductor substrate (2), wherein the electrical contact layer (3.1) is a single-element layer of Al; a functional layer (3.2) arranged directly on the electrical contact layer (3.1), wherein the functional layer (3.2) comprises Ti or a Ti-containing alloy; an adhesive layer (3.3) arranged directly on the functional layer (3.2), wherein the adhesive layer (3.3) comprises Ni; a solder layer (3.4) arranged directly on the adhesive layer (3.3), wherein the solder layer (3.4) is a single-element layer of Sn; a protective layer (43.5) that is arranged directly on the solder layer (3.4).
  2. Coated semiconductor substrate (2,3) according Claim 1 , wherein the protective layer (43.5) comprises an Ag layer or an Au layer.
  3. Coated semiconductor substrate (2,3) according Claim 1 or 2 , wherein the semiconductor substrate (2) has a lower surface comprising an electrical contact terminal formed by a highly doped n + or p + region, and the layer system (3) is arranged on the lower surface of the semiconductor substrate (2).
  4. Coated semiconductor substrate (2,3) according to one of the preceding claims, wherein the semiconductor substrate (2) comprises a vertical transistor structure.
  5. Coated semiconductor substrate (2,3) according to one of the preceding claims, wherein the solder layer (3.4) has a thickness in the range of 1 µm to 5 µm.
  6. Coated semiconductor substrate (2,3) according to one of the preceding claims, wherein the protective layer (43.5) has a thickness in the range of 50 nm to 300 nm.
  7. Coated semiconductor substrate (2,3) according to one of the preceding claims, wherein the adhesive layer (3.3) comprises NiV.
  8. Coated semiconductor substrate (2,3) according to one of the preceding claims, wherein the adhesive layer (3.3) has a thickness in the range of 200 nm to 1 µm.
  9. Coated semiconductor substrate (2,3) according to one of the preceding claims, wherein the electrical contact layer (3.1) has a thickness in the range of 100 nm to 1 µm.
  10. Coated semiconductor substrate (2,3) according to one of the preceding claims, wherein the functional layer (3.2) has a thickness in the range of 50 nm to 200 nm.
  11. Electronic component (10) comprising: a support (1, 41), wherein the surface of the support (1, 41) comprises Cu in a first alternative and Ag in a second alternative; a semiconductor substrate (2) attached to the support (1) by: an electrical contact layer (3.1) arranged directly on the semiconductor substrate (2), wherein the electrical contact layer (3.1) is a single-element layer of Al; a functional layer (3.2) arranged directly on the electrical contact layer (3.1), wherein the functional layer (3.2) comprises Ti or a Ti-containing alloy; an adhesive layer (3.3) arranged directly on the functional layer (3.2), wherein the adhesive layer (3.3) comprises Ni; a first intermetallic phase layer (3.5) arranged directly on the adhesive layer (3.3), wherein the first intermetallic phase layer (3.5) comprises Ni and Sn; and a second intermetallic phase layer (3.6) between the first intermetallic phase layer (3.5) and the surface of the support (1, 41), comprising Cu and Sn in the first alternative and Ag and Sn in the second alternative, wherein a single-element layer of Sn is arranged between the first intermetallic phase layer (3.5) and the second intermetallic phase layer (3.6).
  12. Electronic component (10) according to Claim 11 , wherein the second intermetallic phase layer (3.6) contains traces of Au or Ag.
  13. Electronic component according to one of the Claims 11 or 12 , wherein the semiconductor substrate (2) has a lower surface comprising an electrical contact terminal formed by a highly doped n + or p + region, and the layer system (3) is arranged on the lower surface of the semiconductor substrate (2).
  14. Electronic component according to one of the Claims 11 until 13 , in which the semiconductor substrate (2) comprises a vertical transistor structure.
  15. Electronic component according to one of the Claims 11 until 14 , wherein the adhesive layer (3.3) comprises NiV.
  16. Coated semiconductor substrate (2,3) according to one of the Claims 11 until 15 , wherein the adhesive layer (3.3) has a thickness in the range of 200 nm to 1 µm.
  17. Electronic component according to one of the Claims 11 until 16 , wherein the electrical contact layer (3.1) has a thickness in the range of 100 nm to 1 µm.
  18. Electronic component according to one of the Claims 11 until 17 , wherein the functional layer (3.2) has a thickness in the range of 50 nm to 200 nm.

Description

TECHNICAL AREA The present invention relates to an electronic component and a coated semiconductor substrate. BACKGROUND The production of electronic components very often involves depositing semiconductor chips, semiconductor dies, semiconductor substrates, or semiconductor wafers onto substrates such as leadframes. Currently, the only available highly conductive die mounting material for power semiconductor chips with high temperature cycling resistance and high heat storage reliability is AuSn diffusion solder die mounting. This die mounting material is an AuSn alloy with an Au content of approximately 80%. Due to the high cost, this AuSn solution is limited to a thin solder layer, which typically results in a challenging die mounting process. DE 196 03 654 C1 This concerns a process for soldering a semiconductor body onto a substrate. A disadvantage is that when soldering a nickel layer with tin, the nickel dissolves in the tin. DE 101 24 141 A1 The diagram shows a stack of layers between a semiconductor chip and a substrate designed to absorb thermomechanical stresses between the chip and the substrate, thereby increasing the reliability of the attachment. The substrate is a copper conductor frame. A thick aluminum layer acts as a buffer layer against the chip. DE 10 2005 029 246 A1 The image shows a semiconductor chip soldered to a conductive trace on a substrate via a series of layers. The layer sequence includes barrier layers on both sides of a solder layer. The barrier layers can be made of titanium, vanadium, chromium, or niobium. DE 195 32 250 A1 This concerns diffusion brazing in multilayer structures. A variety of possible material combinations suitable for diffusion brazing, along with their respective melting temperatures, are specified. BRIEF DESCRIPTION OF THE DRAWINGS The accompanying drawings are provided to offer a more detailed understanding of the embodiments. The drawings illustrate embodiments and, together with the description, serve to explain the principles of their design. Other embodiments and many of the intended advantages of the embodiments readily gain in value when better understood with reference to the following detailed description. The elements in the drawings are not necessarily to scale with each other. The same reference numerals denote corresponding similar parts. 1 shows a schematic cross-sectional side view of an electronic component according to the invention; 2a and 2b show schematic cross-sectional side view representations to illustrate essential mechanisms of the bonding process; 3 shows a flowchart to illustrate a method for manufacturing an electronic component according to the invention; and 4 shows a schematic cross-sectional side view of a support and a semiconductor substrate together with a layer stack to illustrate a method for manufacturing an electronic component according to the invention. DETAILED DESCRIPTION OF ILLUSTRATIVE FORM OF EXECUTION The aspects and embodiments are now described with reference to the drawings, in which the same reference numerals are always used to refer generally to the same elements. For explanatory purposes, numerous specific details are listed in order in the following description to provide a thorough understanding of one or more aspects of the embodiments. However, it may be obvious to a person skilled in the art that one or more aspects of the embodiments can also be implemented with a lesser degree of specific detail. In other cases, known structures and elements are shown schematically to facilitate the description of one or more aspects of the embodiments. It is understood that other embodiments may be used and structural or logical modifications may occur without departing from the scope of protection of the present invention. It should also be noted that the drawings are not, or not necessarily, to scale. Even if a particular feature or aspect of an embodiment is disclosed only with reference to one of several implementations, such a feature or aspect may additionally be combined with one or more other features or aspects of the other implementations if this is desirable and advantageous in a particular or specific application. This may be the case. When the terms "contain,""include,""with," or other variations thereof are used in the detailed description or the claims, such terms shall be considered inclusive, similar to the term "comprise." The terms "coupled" and "connected," along with derivatives, may also be used. It is understood that these terms may be used to indicate that two elements cooperate or interact, whether or not they are in direct physical or electrical contact. The term "exemplary" is to be understood merely as an example and not as the best or optimal case. Thus, the following detailed description should not be considered restrictive, and the scope of protection of the present invention is defined by the attached claims. In embodiments of an electronic component and a method for manufact