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DE-102018117698-B4 - Clock circuit and method for its operation

DE102018117698B4DE 102018117698 B4DE102018117698 B4DE 102018117698B4DE-102018117698-B4

Abstract

Clock circuit with: a first latch (201A) configured to generate a first latch output signal (CLK_EN) based on a first control signal (CLKB), an activation signal (CEB) and an output clock signal (CKPB); a second latch (201D) which is connected to the first latch (201A) and is configured to generate the output clock signal (CKPB) in response to a second control signal (CKPI); a first trigger circuit (201C) connected to the first latch (201A) and the second latch (201D) and configured to set the output clock signal (CKPB) in response to at least the first latch output signal (CLK_EN) or a reset signal (RSTCKB); and a clock trigger circuit (110, 201B) which is connected to the first latch (201A) and the first trigger circuit (201C) via a first node (N1) and is configured to generate the first control signal (CLKB) in response to an input clock signal (CLK) and to control the first latch (201A) and the first trigger circuit (201C) based on at least the first control signal (CLKB); wherein the clock trigger circuit (110, 201B) has the following: a first p-transistor (212) with a source connected to a first supply voltage (VDD), a gate configured to receive the input clock signal (CLK), and a drain connected through the first node (N1) to the first latch (201A) and the first trigger circuit (201C); and a first n-transistor (210) with a gate configured to receive the input clock signal (CLK), a source connected to a second supply voltage (VSS) different from the first supply voltage (VDD), and a drain connected through the first node (N1) to the first latch (201A), the first trigger circuit (201C), and the drain of the first p-transistor (212); and/or the first trigger circuit (106, 201C) has the following features: a first n-transistor () with a source connected to the first node (N1), a gate configured to provide the first latch output signal (CLK_EN) receives, and is connected via a second node (N2) to the first latch (201A), and a drain connected to a third node (N3) of the first trigger circuit (201C); and a first p-transistor (216) with a source connected to a fourth node (N4) of the first trigger circuit (201C), a gate configured to receive the input clock signal (CLK), and a drain connected to the drain of the first n-transistor (214) via the third node (N3) of the first trigger circuit (201C).

Inventors

  • Hao-I Yang
  • Cheng Hung Lee
  • Chen-Lin Yang
  • Chiting Cheng
  • Fu-An Wu
  • Yangsyu Lin

Assignees

  • TAIWAN SEMICONDUCTOR MANUFACTURING CO. LTD.

Dates

Publication Date
20260513
Application Date
20180723
Priority Date
20180719

Claims (15)

  1. Clock circuit comprising: a first latch (201A) configured to generate a first latch output signal (CLK_EN) based on a first control signal (CLKB), an activation signal (CEB), and an output clock signal (CKPB); a second latch (201D) connected to the first latch (201A) and configured to generate the output clock signal (CKPB) in response to a second control signal (CKPI); a first trigger circuit (201C) connected to the first latch (201A) and the second latch (201D) and configured to set the output clock signal (CKPB) in response to at least the first latch output signal (CLK_EN) or a reset signal (RSTCKB); and a clock trigger circuit (110, 201B) connected via a first node (N1) to the first latch (201A) and the first trigger circuit (201C) and configured to generate the first control signal (CLKB) in response to an input clock signal (CLK) and to control the first latch (201A) and the first trigger circuit (201C) based on at least the first control signal (CLKB); wherein the clock trigger circuit (110, 201B) comprises: a first p-transistor (212) with a source connected to a first supply voltage (VDD), a gate configured to receive the input clock signal (CLK), and a drain connected via the first node (N1) to the first latch (201A) and the first trigger circuit (201C); and a first n-transistor (210) with a gate configured to receive the input clock signal (CLK), a source connected to a second supply voltage (VSS) different from the first supply voltage (VDD), and a drain connected through the first node (N1) to the first latch (201A), the first trigger circuit (201C), and the drain of the first p-transistor (212); and/or where the first trigger circuit (106, 201C) comprises: a first n-transistor () with a source connected to the first node (N1), a gate configured to receive the first latch output signal (CLK_EN), and connected to the first latch (201A) via a second node (N2), and a drain connected to a third node (N3) of the first trigger circuit (201C); and a first p-transistor (216) with a source connected to a fourth node (N4) of the first trigger circuit (201C), a gate configured to receive the input clock signal (CLK), and a drain connected to the drain of the first n-transistor (214) via the third node (N3) of the first trigger circuit (201C).
  2. Clock circuit according to Claim 1 , wherein the first trigger circuit (201C) further comprises: a second p-transistor (218) with a source connected to the fourth node (N4) of the first trigger circuit (201C), a gate configured to receive the first latch output signal (CLK_EN), and a drain connected through the third node (N3) of the first trigger circuit (201C) to the drain of the first n-transistor (214) and the drain of the first p-transistor (216).
  3. Clock circuit according to Claim 2 , wherein the first trigger circuit (201C) further comprises: a second n-transistor (222) with a source connected to the second latch (201D), a gate configured to receive the reset signal (RSTCKB), and a drain connected to the third node (N3) of the first trigger circuit (201C); and a third p-transistor (220, 402) with a source connected to a first supply voltage (VDD), a gate configured to receive the reset signal (RSTCKB), and a drain connected by the third node (N3) of the first trigger circuit (201C) to the drain of the second n-transistor (222), or a drain connected by the fourth node (N4) of the first trigger circuit (201C) to the source of the first p-transistor (216).
  4. Clock circuit according to one of the preceding claims, wherein the first latch (201A) comprises a logic OR gate (204) having: a first input terminal configured to receive the first control signal (CLKB) and connected to at least the first node (N1); a second input terminal configured to receive the first latch output signal (CLK_EN) and connected to at least one second node (N2) is connected; and an output terminal configured to output an OR output signal based on the first latch output signal (CLK_EN) and the first control signal (CLKB).
  5. Clock circuit according to one of the preceding claims, wherein the first latch (201A) further comprises a logic NAND gate (206) having: a first input terminal connected to the output terminal of the logic OR gate (204), wherein the first input terminal of the logic NAND gate (206) is configured to receive the OR output signal; a second input terminal configured to receive an inverted second control signal (CKPBI); and an output terminal configured to output a first NAND output signal based on the inverted second control signal (CKPBI) and the OR output signal.
  6. Clock circuit according to Claim 5 , wherein the first latch (201A) further comprises a logical NOR gate (208) having: a first input terminal configured to receive the activation signal (CEB); a second input terminal configured to receive the first NAND output signal and connected to the output terminal of the logical NAND gate (206); and an output terminal configured to output the first latch output signal (CLK_EN) based on the activation signal (CEB) and the first NAND output signal, wherein the output terminal of the logical NOR gate (208) is connected to at least the second node (N2) and the logical NOR gate (208) is configured to set a voltage of the second node (N2), the voltage of the second node (N2) being equal to the first latch output signal (CLK_EN).
  7. Clock circuit according to one of the preceding claims, wherein the second latch (201D) has an inverter (228) with an input terminal and an output terminal, wherein the input terminal of the inverter (228) is configured to receive the output clock signal (CKPB) and is connected to a third node (N3) of the first trigger circuit (201C), and the output terminal of the inverter (228) is configured to output the second control signal (CKPI) in response to the output clock signal (CKPB).
  8. Clock circuit according to Claim 7 , wherein the second latch (201D) further comprises: a first p-transistor (224) with a source connected to a first supply voltage (VDD), a drain connected to a fourth node (N4) of the first trigger circuit (201C), and a gate connected to the output terminal of the inverter (228) and configured to receive the second control signal (CKPI); and a first n-transistor (226) with a source connected to a second supply voltage (VSS) different from the first supply voltage (VDD), a drain connected to the third node of the first trigger circuit (201C), and a gate connected to the output terminal of the inverter (228) and configured to receive the second control signal (CKPI).
  9. Clock circuit comprising: a first latch (201A) configured to generate a first latch output signal (CLK_EN) based on a first control signal (CLKB), an activation signal (CEB), and an output clock signal (CKPB); a second latch (201D) connected to the first latch (201A) and configured to generate the output clock signal (CKPB) in response to a second control signal (CKPI); a first trigger circuit (201C) connected to the first latch (201A) and the second latch (201D) and configured to set the output clock signal (CKPB) in response to at least the first latch output signal (CLK_EN) or a reset signal (RSTCKB); a clock trigger circuit (110, 201B) which is connected by a first node (N1) to the first latch (201A) and the first trigger circuit (201C) and is configured to generate the first control signal (CLKB) in response to a first clock signal with a first voltage swing and to control the first latch (201A) and the first trigger circuit (201C) on the basis of at least the first clock signal; and a level shift circuit (600) which is connected at least to the clock trigger circuit (110, 201B) and is configured to generate a second clock signal with a second voltage swing that is different from the first voltage swing of the first clock signal. wherein the clock trigger circuit comprises: a first n-transistor (210) with a source connected to a supply voltage (VSS), a gate configured to receive the first clock signal, and a drain connected by the first node (N1) to the first latch (201A) and the first trigger circuit (201C) bound; and a second n-transistor (502) with a source connected to at least the second supply voltage (VSS), a gate configured to receive the second clock signal, and a drain connected through the first node (N1) to the first latch (201A), the first trigger circuit (201C), and the drain of the first n-transistor (210); a first p-transistor (506) with a source connected to a first supply voltage (VDDM) different from the second supply voltage (VSS), and a gate configured to receive the first clock signal; and a second p-transistor (504) with a source connected to a drain of the first p-transistor (506), a gate configured to receive the second clock signal, and a drain connected through the first node (N1) to the first latch (201A), the first trigger circuit (201C), the drain of the first n-transistor (210), and the drain of the second n-transistor (502); or wherein the first trigger circuit comprises: a first n-transistor (214) with a source connected to the first node (N1), a gate configured to receive the first latch output signal (CLK_EN), and connected through a second node (N2) to the first latch (201A), and a drain connected to a third node (N3) of the first trigger circuit (201C); and a first p-transistor (216) with a gate configured to receive the first clock signal and a drain connected to the drain of the first n-transistor (214) via the third node (N3) of the first trigger circuit (201C).
  10. Clock circuit according to Claim 9 , wherein the first trigger circuit (201C) further comprises: a second p-transistor (510) with a source connected to a fourth node (N4) of the first trigger circuit (201C), a gate configured to receive the second clock signal, and a drain connected to a source of the first p-transistor (216); and a third p-transistor (218) with a source connected through the fourth node (N4) of the first trigger circuit (201C) to the source of the second p-transistor (510), a gate configured to receive the first latch output signal (CLK_EN), and a drain connected through the third node (N3) of the first trigger circuit (201C) to the drain of the first n-transistor (214) and the drain of the first p-transistor (216).
  11. Clock circuit according to Claim 10 , wherein the first trigger circuit (201C) further comprises: a second n-transistor (222) with a source connected to the second latch (201D), a gate configured to receive the reset signal (RSTCKB), and a drain connected to the third node (N3) of the first trigger circuit (201C); and a fourth p-transistor (520, 802) with a source connected to a first supply voltage (VDDM), a gate configured to receive the reset signal (RSTCKB), and either a drain connected through the third node (N3) of the first trigger circuit (201C) to the drain of the second n-transistor (222), or a drain connected through the fourth node (N4) of the first trigger circuit (201C) to the source of the second p-transistor (510) and the source of the third p-transistor.
  12. Method for operating a clock circuit comprising the following steps: Receiving a first clock signal with a clock trigger circuit (110, 201B); Causing a first latch (201A), a first latch output signal (CLK_EN), to transition from the first voltage level (VSS) to the second voltage level (VDD) by means of a first latch (201A), in response to a transition of an activation signal (CEB) from a second voltage level (VDD) to a first voltage level (VSS), wherein the second voltage level (VDD) is different from the first voltage level (VSS); Causing the clock trigger circuit (110, 201B), in response to a transition of the first clock signal from the first voltage level (VSS) to the second voltage level (VDD), to pull a first node (N1) from the second voltage level (VDD) to the first voltage level (VSS), wherein the pulling of the first node (N1) causes a first control signal (CLKB) of the clock trigger circuit (110, 201B) to go from the second voltage level (VDD) to the first voltage level (VSS), wherein the clock trigger circuit (110, 201B) is connected through the first node (N1) to an input of a first latch (201A) and a first trigger circuit (201C), and the first control signal (CLKB) is fed back from the clock trigger circuit (110, 201B) to the input of the first latch (201A) from the first node (N1); and cause, through the first trigger circuit (201C), an output clock signal (CKPB), in response to the transition of the first clock signal to the second voltage level (VDD) and in Response to the transition of the first latch output signal (CLK_EN) to the second voltage level (VDD), to transition from the second voltage level (VDD) to the first voltage level (VSS).
  13. Procedure according to Claim 12 , which further includes: causing a reset signal (RSTCKB) to transition from the second voltage level (VDD) to the first voltage level (VSS) in response to the transition of the output clock signal (CKPB) from the second voltage level (VDD) to the first voltage level (VSS); causing the output clock signal (CKPB) to transition from the first voltage level (VSS) to the second voltage level (VDD) in response to the transition of the reset signal (RSTCKB) from the second voltage level (VDD) to the first voltage level (VSS); and causing the reset signal (RSTCKB) to transition from the first voltage level (VSS) to the second voltage level (VDD) in response to the transition of the output clock signal (CKPB) from the first voltage level (VSS) to the second voltage level (VDD).
  14. Procedure according to Claim 13 , wherein causing the output clock signal (CKPB) by the first trigger circuit (201C) to transition from the second voltage level (VDD) to the first voltage level (VSS) comprises: causing a first n-transistor (214) to turn on in response to the first latch output signal (CLK_EN) such that a third node (N3) is connected to the first node (N1) and the third node (N3) is pulled to the first voltage level (VSS), and causing the output clock signal (CKPB) by the first trigger circuit (201C) to transition from the first voltage level (VSS) to the second voltage level (VDD) in response to the transition of the reset signal (RSTCKB) from the second voltage level (VDD) to the first voltage level (VSS) comprises: causing a second n-transistor (222) to turn on in response to the transition of the reset signal from the second voltage level (VDD) to switch off to the first voltage level (VSS), so that the third node (N3) is disconnected by a third n-transistor (226); and causing a third p-transistor (220) to switch on in response to the transition of the reset signal (RSTCKB) from the second voltage level (VDD) to the first voltage level (VSS), so that the third node (N3) is pulled to the second voltage level (VDD) of a first supply voltage (VDD).
  15. Procedure according to Claim 13 or 14 , wherein causing the reset signal (RSTCKB) to transition from the first voltage level (VSS) to the second voltage level (VDD) in response to the transition of the output clock signal (CKPB) from the first voltage level (VSS) to the second voltage level (VDD) comprises: causing the second n-transistor (222) to turn on in response to the transition of the reset signal (RSTCKB) from the first voltage level (VSS) to the second voltage level (VDD), so that the third node (N3) is connected to the third n-transistor (226); and causing the first p-transistor (220) to turn off in response to the transition of the reset signal (RSTCKB) from the first voltage level (VSS) to the second voltage level (VDD), so that the third node (N3) is disconnected from the first supply voltage (VDD).

Description

background The semiconductor integrated circuit (IC) industry has produced a wide range of digital components to address problems in various fields. Some of these digital components, such as clock circuits, are designed to generate one or more clock signals. As ICs have become smaller and more complex, the operating voltages of these digital components have decreased, impacting IC performance. The US 2015 / 0 365 080 A1 Disclosing a method for generating a clock pulse, receiving a leading edge at a clock input at a time when an enable signal is active, generating a leading edge at a clock output based on the received leading edge at the clock input, buffering a logic value corresponding to the leading edge at the clock output, preventing changes at the clock input from affecting the buffered logic value after the logic value has been buffered, resetting the buffered logic value after an initial delay, and retaining the reset logic value until a second leading edge at the clock input is received. The second leading edge at the clock input corresponds to the leading edge at the clock input. Further prior art is disclosed in the US 2014 / 0 253 201 A1 known. The invention is defined in the claims. Brief description of the drawings Aspects of the present invention are best understood with reference to the detailed description below in conjunction with the accompanying drawings. It should be noted that, in accordance with common industry practice, various elements are not drawn to scale. Rather, for the sake of clarity of discussion, the dimensions of the various elements may be arbitrarily enlarged or reduced. 1 is a block diagram of a clock circuit according to some embodiments. 2 is a circuit diagram of a clock circuit according to some embodiments. 3 is a timing diagram of different signals from a clock circuit according to some embodiments. 4 is a circuit diagram of a clock circuit according to some embodiments. 5 is a timing diagram of different signals from a clock circuit according to some embodiments. 6 This is a circuit diagram of a level-shifting circuit according to some embodiments. 7 is a timing diagram of different signals from a clock circuit according to some embodiments. 8 is a circuit diagram of a clock circuit according to some embodiments. The 9A and 9B are a flowchart of a procedure for operating a clock circuit, such as the clock circuit of 1 , 2 , 4 , 5 or 8 , according to some embodiments. Detailed description The following description provides many different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components, materials, values, steps, arrangements, etc., are described below to simplify the present invention. Other components, materials, values, steps, arrangements, etc., are also considered. For example, the fabrication of a first element over or on top of a second element in the following description may include embodiments in which the first and second elements are fabricated in direct contact, and it may also include embodiments in which additional elements can be fabricated between the first and second elements such that the first and second elements are not in direct contact. Furthermore, reference numerals and/or letters may be repeated in the various examples in the present invention. This repetition is for the sake of simplicity and clarity and does not, in itself, imply any relationship between the various embodiments and/or configurations discussed. Furthermore, spatially relative terms, such as "located below,""under,""lower,""locatedabove,""upper," and the like, can be used here to simply describe the relationship of an element or structure to one or more other elements or structures depicted in the figures. In addition to the orientation shown in the figures, these spatially relative terms should encompass other orientations of the component in use or operation. The component can be oriented differently. The images can be rotated (by 90 degrees or in another orientation), and the spatially relative descriptors used here can be interpreted accordingly. According to some embodiments, a clock circuit comprises a first latch, a second latch, a first trigger circuit, and a clock trigger circuit. The first latch is configured to generate a first latch output signal in response to a first control signal, an activation signal, and an output clock signal. The second latch is connected to the first latch and is configured to generate the output clock signal in response to a second control signal. The first trigger circuit is connected to the first and second latches and is configured to set the output clock signal in response to at least the first latch output signal or a reset signal. The clock trigger circuit is connected to the first latch and the first trigger circuit via a first node and is configured to generate the first control signal in response to an input clock signal and to control the first latch and