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DE-102018209597-B4 - TRANSISTOR ELEMENT WITH A BURIED INSULATING LAYER WITH ADDED FUNCTION

DE102018209597B4DE 102018209597 B4DE102018209597 B4DE 102018209597B4DE-102018209597-B4

Abstract

Transistor element (100A), with a channel region (131) formed in a semiconductor layer (130, 130N, 130P) and arranged laterally between a drain region (133) and a source region (132); a control gate electrode structure (120) formed on the channel region (131); a buried insulating layer stack (110) formed below the semiconductor layer (131) comprising at least two different dielectric material layers (111, 113) and a charge-trapping layer (112); and a semiconductor body region (102N, 102P) formed below the buried insulating layer stack (110) and connected to receive a control voltage, wherein the semiconductor body region (102N, 102P) comprises a doped region (102N) for setting a type of charge carrier to be trapped in the charge-trapping layer (112) and the semiconductor body region (102N, 102P) has a further doped region (102P) for setting a type of charge carrier to be trapped in the charge-capture layer (112), wherein the further doped region (102P) is of inverse conductivity type compared to the doped region (102N).

Inventors

  • Ralf Richter
  • Jochen Willi. Poth
  • Sven Beyer
  • Stefan Duenkel

Assignees

  • GLOBALFOUNDRIES U.S. INC.

Dates

Publication Date
20260513
Application Date
20180614
Priority Date
20170614

Claims (8)

  1. Transistor element (100A), comprising: a channel region (131) formed in a semiconductor layer (130, 130N, 130P) and arranged laterally between a drain region (133) and a source region (132); a control gate electrode structure (120) formed on the channel region (131); a buried insulating layer stack (110) formed below the semiconductor layer (131) comprising at least two different dielectric material layers (111, 113) and a charge-trapping layer (112); and a semiconductor body region (102N, 102P) formed below the buried insulating layer stack (110) and connected to receive a control voltage, whereby the semiconductor body region (102N, 102P) comprises a doped region (102N) for setting a type of charge carrier to be trapped in the charge-trapping layer (112) and the semiconductor body region (102N, 102P) has a further doped region (102P) for setting a type of charge carrier to be trapped in the charge-trapping layer (112), and wherein the further doped region (102P) is of inverse conductivity type compared to the doped region (102N).
  2. Transistor element according to Claim 1 , wherein the charge-trapping layer (112) contains nitrogen and/or hafnium.
  3. Transistor element according to Claim 1 , wherein the buried insulating layer stack (110) further comprises a dielectric blocking layer (113) designed to separate the charge-trapping layer (112) from the semiconductor layer (130).
  4. Transistor element according to Claim 1 , wherein the buried insulating layer stack (110) further comprises a charge tunnel layer (111) which is designed in such a way that it allows charge carriers to tunnel through it and separates the charge-capture layer (112) from the semiconductor body region (102P, 102N).
  5. Transistor element according to Claim 1 , wherein the buried insulating layer stack (110) comprises at least one dielectric layer with a large dielectric constant (113) containing a dielectric material with a large dielectric constant.
  6. Transistor element according to Claim 5 , wherein the buried insulating layer stack (110) further comprises two or more dielectric layers (112, 113) without a large dielectric constant, which contain a dielectric material with a dielectric constant of 10 or less.
  7. Transistor element according to Claim 5 , wherein the thickness of the at least one dielectric layer with a large dielectric constant (113) is greater than the thickness of any dielectric layer without a large dielectric constant of the buried insulating layer stack (110).
  8. Transistor element according to Claim 7 , wherein a combined thickness of the at least one dielectric layer with a large dielectric constant (113) is greater than a combined thickness of all dielectric layers without a large dielectric constant of the buried insulating layer stack.

Description

BACKGROUND 1. AREA OF REVELATION The present disclosure relates generally to semiconductor devices with transistor elements that are manufactured on the basis of an SOI (semiconductor-on-insulator) architecture, i.e., which have a buried insulating layer. 2. DESCRIPTION OF THE STATE OF THE ART Significant progress has been made in the field of semiconductor devices, particularly with regard to small-signal processing and power applications. In particular, the continuous scaling of critical semiconductor device dimensions has contributed to remarkable improvements in the overall complexity of analog and digital circuits, such as microcontrollers, CPUs, GPUs, and the like. Complex microprocessors can contain up to several hundred million or even over a billion individual transistor elements forming one or more complex circuits. In addition to the continuous reduction of the critical dimensions of transistor elements that form the backbone of complex circuits, various other aspects have been considered to promote improved performance. For example, when attempting to further enhance certain aspects of circuit behavior, such as signal processing speed, power consumption, information density, processability, and the like, different approaches have been pursued to address these diverse aspects. For example, if critical dimensions of field-effect transistors, such as the gate length, are continuously reduced—currently on the order of 30 nm or less in demanding small-signal applications—then certain measures must be implemented to combat various negative effects associated with the reduced gate length. In this respect, reduced channel controllability for small channel lengths, fluctuations in dopant concentration in channel regions, and the like can represent some of these adverse effects that must be addressed to fully exploit the advantages associated with a reduced gate length. Similarly, with regard to reduced overall power consumption, static and dynamic leakage currents can increasingly lead to undesirable transistor behavior. Regarding some of the side effects of reducing critical transistor dimensions, certain approaches have been pursued, leading to more advanced and complex integrated circuits. However, each of these diverse approaches can still introduce certain disadvantages, while offering better results in other aspects related to the aforementioned side effects. For example, three-dimensional transistor architectures have been developed to provide improved channel controllability and increased forward current without unnecessarily affecting or further reducing the overall transistor dimensions. On the other hand, such solutions can significantly contribute to overall process complexity, making these approaches less desirable for applications requiring low cost at high circuit complexity. In other approaches, the well-established planar transistor configuration can be used in highly complex circuit designs with gate lengths in the aforementioned range. A so-called "SOI" (silicon-on-insulator) configuration is often employed in an attempt to improve overall performance and extend the applicability of the planar architecture to even further reduced transistor dimensions. In general, an SOI architecture can be advantageous in terms of reducing the overall parasitic capacitance of the transistor's semiconductor body. This is because the semiconductor area containing the drain, source, and channel regions is bounded vertically (i.e., along the depth direction) by a buried insulating material, thus generally reducing the transistor size along the vertical direction compared to a full-substrate configuration. Furthermore, in current developments, the thickness of the base semiconductor material of an SOI transistor is significantly smaller, for example, down to 15 nm and considerably less, to achieve an essentially depleted transistor configuration, which in particular contributes to improved channel controllability. Additionally, the dopant concentration in the channel region can be significantly reduced, or the channel region can be implemented as an essentially undoped material, resulting in significantly lower power fluctuations. These fluctuations are typically attributed to the unavoidable dopant concentration variations in devices requiring substantial channel doping. Furthermore, with regard to channel controllability, which can be significantly improved by using a three-dimensional transistor architecture, it was recognized that the controllability of the channel region can also be improved in the planar transistor configuration by A configuration is provided that allows the application of a "bias" applied to a transistor region capacitively coupled to the channel regions of the transistor under consideration. It turns out that transistor elements fabricated based on the concept of a SOl architecture are particularly well-suited for applying a backside bias, since the channel region is electrically i