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DE-102019201911-B4 - Comparator with dual, alternately used transistors and imaging device

DE102019201911B4DE 102019201911 B4DE102019201911 B4DE 102019201911B4DE-102019201911-B4

Abstract

Comparator (116), comprising: two entrances (140, 142) and one exit (144); a first pair of transistors (130, 132) connected to a first input (140) of the two inputs (140, 142); a second pair of transistors (134, 136) connected to a second input (142) of the two inputs (140, 142), wherein the first pair of transistors (130, 132) and the second pair of transistors (134, 136) are connected to the output (144); a first signal generator (146) connected to a first transistor (130, 136) of each of the first pair of transistors (130, 132) and the second pair of transistors (134, 136); and a second signal generator (148) connected to a second transistor (132, 134) of each of the first pair of transistors (130, 132) and the second pair of transistors (134, 136), wherein the first signal generator (146) and the second signal generator (148) are connected to the substrate gates (154) of transistors in the first pair of transistors (130, 132) and the second pair of transistors (134, 136). wherein the first signal generator (146) and the second signal generator (148) output on/off control signals (VBG_0, VBG_1) which have timing patterns that are inverted relative to each other, causing only the first transistor (130, 134) or the second transistor (132, 136) in each of the first pair of transistors (130, 132) and the second pair of transistors (134, 136) to be active at any given time, and where an active transistor in the first pair of transistors (130, 132) and an active transistor in the second pair of transistors (134, 136) amplify the difference between the two inputs (140, 142) through the output.

Inventors

  • Thomas G. McKay

Assignees

  • GLOBALFOUNDRIES U.S. INC.

Dates

Publication Date
20260513
Application Date
20190214
Priority Date
20180323

Claims (12)

  1. Comparator (116) comprising: two inputs (140, 142) and one output (144); a first pair of transistors (130, 132) connected to a first input (140) of the two inputs (140, 142); a second pair of transistors (134, 136) connected to a second input (142) of the two inputs (140, 142), the first pair of transistors (130, 132) and the second pair of transistors (134, 136) being connected to the output (144); a first signal generator (146) connected to a first transistor (130, 136) of each of the first pair of transistors (130, 132) and the second pair of transistors (134, 136); and a second signal generator (148) connected to a second transistor (132, 134) of each of the first pair of transistors (130, 132) and the second pair of transistors (134, 136), whereby the first signal generator (146) and the second signal generator (148) are connected to the substrate gates (154) of transistors in the first pair of transistors (130, 132) and the second pair of transistors (134, 136). wherein the first signal generator (146) and the second signal generator (148) output on/off control signals (VBG_0, VBG_1) which have timing patterns that are inverted relative to each other, causing only the first transistor (130, 134) or the second transistor (132, 136) in each of the first pair of transistors (130, 132) and the second pair of transistors (134, 136) to be active at any given time, and where an active transistor in the first pair of transistors (130, 132) and an active transistor in the second pair of transistors (134, 136) amplify the difference between the two inputs (140, 142) by the output.
  2. Comparator (116) according to Claim 1 , wherein the first signal generator (146) and the second signal generator (148) output the on/off control signals (VBG_0, VBG_1) with a relative offset to each other, causing at least two of the four transistors (130, 132, 134, 136) in the first pair of transistors (130, 132) and the second pair of transistors (134, 136) to be active at any one time.
  3. Comparator (116) according to Claim 2 , where the offset is equal to a time period for the transistors in the first pair of transistors (130, 132) and the second pair of transistors (134, 136) in which they transition from an inactive state to an active state.
  4. Comparator (116) according to Claim 1 , wherein the on/off control signals (VBG_0, VBG_1) cause: only the first transistor (130) or the second transistor (132) in the first pair of transistors (130, 132) to be active at any given time; and only the first transistor (134) or the second transistor (136) in the second pair of transistors (134, 136) to be active at any given time.
  5. Comparator (116) according to Claim 1 , wherein the transistors (130, 132, 134, 136) in the first pair of transistors (130, 132) and the second pair of transistors (134, 136) have charge traps that accumulate fault charges over a charge accumulation period, wherein the fault charges cause a malfunction of the transistors (130, 132, 134, 136) and wherein the first signal generator (146) and the second signal generator (148) continuously output an on signal for a shorter time than the charge accumulation period.
  6. Comparator (116) according to Claim 5 , wherein the on/off control signals (VBG_0, VBG_1) provide a connection to earth at intervals shorter than the charge accumulation period, wherein the charge traps are periodically discharged to earth at intervals shorter than the charge accumulation period, and wherein the fault charges are prevented from accumulating in the charge traps.
  7. Imaging device (100) comprising: a pixel array (114); a comparator (116) electrically connected to the pixel array (114) and receiving its output; a counter (118) electrically connected to the comparator (116) and receiving its output, wherein the counter (118) digitally samples the output of the comparator (118) and generates a digital output; and latches electrically connected to the counter (118) and receiving the digital output, wherein the comparator (116) comprises: two inputs (140, 142) and one output (144); a first pair of transistors (130, 132) connected to a first input (140) of the two inputs (140, 142); a second pair of transistors (134, 136) connected to a second input (142) of the two inputs (140, 142), the first pair of transistors (130, 132) and the second pair of transistors (134, 136) being connected to the output (144); a first signal generator (146) connected to a first transistor (130, 134) in each of the first pair of transistors (130, 132) and the second pair of transistors (134, 136); and a second signal generator (148) connected to a second transistor (132, 136) in each of the first pair of transistors (130, 132) and the second pair of transistors (134, 136), wherein the first signal generator (146) and the second signal generator (148) are connected to the substrate gates of transistors of the first pair of transistors (130, 132) and the second pair of transistors (134, 136). wherein the first signal generator (146) and the second signal generator (148) output on/off control signals (VBG_0, VBG_1) which have time patterns that are inverted relative to each other, causing only the first transistor (130, 134) or the second transistor (132, 136) in each of the first pair of transistors (130, 132) and the second pair of transistors (134, 136) to be active at any given time, and wherein an active transistor in the first pair of transistors (130, 132) and an active transistor in the second pair of transistors (134, 136) amplify the difference between the two inputs (140, 142) by the output (144).
  8. Imaging device (100) according to Claim 7 , wherein the first signal generator (146) and the second signal generator (148) output the on/off control signals (VBG_0, VBG_1) offset from each other, causing at least two of the four transistors (130, 132, 134, 136) in the first pair of transistors (130, 132) and the second pair of transistors (134, 136) to be active at any one time.
  9. Imaging device (100) according to Claim 8 , where the offset is equal to a time period in which the transistors (130, 132, 134, 136) of the first pair of transistors (130, 132) and the second pair of transistors (134, 136) transition from an inactive state to an active state.
  10. Imaging device (100) according to Claim 7 , wherein the on/off control signals (VBG_0, VBG_1) cause: only the first transistor (130) or the second transistor (132) of the first pair of transistors (130, 132) to be active at any given time; and only the first transistor (134) or the second transistor (136) in the second pair of transistors (134, 136) to be active at any given time.
  11. Imaging device (100) according to Claim 7 , wherein transistors (130, 132, 134, 136) of the first pair of transistors (130, 132) and the second pair of transistors (134, 136) have charge traps that accumulate fault charges over a charge accumulation period, wherein the fault charges cause a malfunction of the transistors (130, 132, 134, 136), and wherein the first signal generator (146) and the second signal generator (148) continuously output an on signal for less time than the charge accumulation period.
  12. Imaging device (100) according to Claim 11 , wherein the on/off control signals (VBG_0, VBG_1) provide a connection to ground at intervals shorter than the charge accumulation time, wherein the charge traps are periodically discharged to ground at intervals shorter than the charge accumulation time, preventing the fault charges from accumulating in the charge traps.

Description

Field of invention The present invention relates to comparators (operational amplifiers) and in particular comparators with dual, alternately used transistors, and an imaging device therewith. Description of the state of the art Integrated circuit devices, such as imaging devices, use transistors for many different functions. These transistors can take many different forms, from planar transistors to vertical transistors to transistors that use a "fin" structure. Generally, for example, pairs of transistors in imaging devices are used connected to pixel arrays to form comparators. These comparators, in combination with a clock signal, are used to record information from the pixel array into latches. However, such comparators can sometimes produce faulty signals. For example, during steady-state channel inversion, random time-step patterns may appear in the signals output by the comparators. Physically, this can be attributed to a limited number of deep-energy-level traps in the comparator transistors. A relatively large spacing may be observed between such step patterns. These step patterns are sometimes referred to as Random Telegraph Noise (RTN). A well-known way to improve RTN is to reduce defects in the manufacturing process of the transistors used in the comparators. The document US 2005 / 0 248 383 A1 This relates to a pulse-division multiplexed output subsystem. In a particular embodiment, the output system can comprise a plurality of pulse generators, a first pair of transistors, and a second pair of transistors, wherein each transistor of the first pair is connected to one of the pulse generators of the first pair, and each transistor of the second pair is connected to one of the pulse generators of the second pair. The output subsystem can further comprise a first pair of resistive loads, wherein each of the resistive loads of the first pair is connected to one of the two transistors of the first pair and to one of the two transistors of the second pair, as well as a first current source connected to the first and second transistor pairs. The document JP 2018 - 37 924 A relates to a semiconductor device comprising a differential input circuit with a first input transistor and a second input transistor forming a differential pair; and a tuning circuit capable of changing the magnitude of the first or second input transistor by setting the connection state of a plurality of transistors for the purpose of configuring the first or second input transistor. Summary The invention comprises a comparator and an image sensor (e.g., an image sensor device) which, among other components, includes a pixel array, comparators, counters, latches, etc. The pixel array can, for example, be an arrangement of complementary metal-oxide-semiconductor (CMOS) sensors. The comparators can be operational amplifier-type comparators that are electrically connected to the pixel array and receive an output from it. The counters are electrically connected to the comparators and receive an output from them. The counters digitally sample the output of the comparators and generate a digital output. The latches are electrically connected to the counters and receive their digital output. The comparators according to the invention comprise (among other components) two inputs, one output, and two pairs of transistors. A first pair of transistors is connected to the first input of the two inputs, and a second pair of transistors is connected to the second input. Both pairs of transistors are connected to the output. Additionally, in each pair of transistors, a first signal generator is connected to the first transistor, and in each pair of transistors, a second signal generator is connected to the second transistor. In particular, the first signal generator and the second signal generator are connected to the suspend gates of the transistors in the pairs of transistors. The first and second signal generators output on/off control signals with inverted timing patterns relative to each other. This causes only the first or second transistor of each pair of transistors to be active at any given time (with minimal overlap). Thus, the single active transistor in the first pair of transistors and the single active transistor in the second pair of transistors amplifies the difference between the two inputs through the output. In other words, the on/off control signals cause only the first or second transistor of the first pair to be active at any given time. A pair of transistors is active, and only the first transistor or the second transistor of the second pair of transistors is active at any given time. The first signal generator and the second signal generator are connected to the substrate gates of transistors in the first and second pair of transistors, respectively. The first and second signal generators also output the on/off control signals with a relative offset. This ensures that at least two of the four transistors (one from the fi