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DE-102020107939-B4 - Integrated chip with memory cell with magnetic access selection device and method for its manufacture

DE102020107939B4DE 102020107939 B4DE102020107939 B4DE 102020107939B4DE-102020107939-B4

Abstract

Integrated chip, featuring: an MTJ device (109) with a first electrode (105, 108) and a second electrode (105, 108); and an access selection device (101) for the MTJ device (109) comprising a first metal structure (104) and a second metal structure (102) separated from each other by several non-metallic layers (103); wherein one of the first metal structure (104) and the second metal structure (102) is coupled to the second electrode (105, 108); and the first metal structure (104) has a polarized ferromagnetic layer, wherein the first metal structure (104) is an electrode for the access selection device (101), wherein the access selection device (101) is a bipolar selection switch, wherein the several non-metallic layers (103) have two insulators (103a, 103b) with different band gap energies, wherein one insulator (103b) of the two insulators (103a, 103b) which have different band gap energies is an oxide of a metal of the polarized ferromagnetic layer and is directly adjacent to the polarized ferromagnetic layer.

Inventors

  • Mauricio Manfrini

Assignees

  • TAIWAN SEMICONDUCTOR MANUFACTURING CO. LTD.

Dates

Publication Date
20260513
Application Date
20200323
Priority Date
20200320

Claims (14)

  1. Integrated chip comprising: an MTJ device (109) with a first electrode (105, 108) and a second electrode (105, 108); and an access selection device (101) for the MTJ device (109), which has a first metal structure (104) and a second metal structure (102) separated from each other by several non-metallic layers (103); wherein one of the first metal structure (104) and one of the second metal structure (102) is coupled to the second electrode (105, 108); and the first metal structure (104) has a polarized ferromagnetic layer, wherein the first metal structure (104) is an electrode for the access selection device (101), whereby the access selection device (101) is a bipolar selector switch, whereby the multiple non-metallic layers (103) have two insulators (103a, 103b) with different bandgap energies, whereby one insulator (103b) of the two insulators (103a, 103b) having different bandgap energies is an oxide of a metal of the polarized ferromagnetic layer and is directly adjacent to the polarized ferromagnetic layer.
  2. Integrated chip according to Claim 1 , wherein the MTJ component (109) and the access selection device (101) are formed by a stack of material layers.
  3. Integrated chip according to Claim 2 , wherein the polarized ferromagnetic layer has a polarization parallel to a plane of the polarized ferromagnetic layer.
  4. Integrated chip according to Claim 3 , wherein the MTJ device (109) has a fixed layer with perpendicular magnetic polarization.
  5. Integrated chip according to one of the preceding claims, wherein the first metal structure (104) has an electrode layer that is different from the polarized ferromagnetic layer.
  6. Integrated chip according to one of the preceding claims, wherein the polarized ferromagnetic layer is configured such that it tilts a direction of polarization of a free layer of the MTJ device (109).
  7. Integrated chip according to one of the preceding claims, wherein: the MTJ device (109) has a free layer and a fixed layer; and the polarized ferromagnetic layer is configured such that it has a magnetic field which extends through the free layer in such a way as to reduce the switching time for the MTJ device (109).
  8. Integrated chip comprising: a magnetic MTJ device (109) arranged within a dielectric structure (304) over a substrate (302), wherein the MTJ device (109) has an MTJ arranged between a first MTJ electrode (105, 108) and a second MTJ electrode (105, 108); and a bipolar selector switch, BS, (101) comprising a middle structure (103) arranged between a first BS electrode (104) and a second BS electrode (102), the second BS electrode (102) being coupled to or an integral part of the first MTJ electrode (105, 108), the middle structure (103) comprising multiple layers of insulators, two of which (103a, 103b) have different bandgap energies, and one of the first BS electrode (104) and the second BS electrode (102) comprising a polarized magnetic layer, the layer (103b) of the multiple layers of insulators directly adjacent to the polarized magnetic layer being an oxide of a metal of the polarized magnetic layer.
  9. Integrated chip according to Claim 8 , wherein the polarized magnetic layer has a polarization parallel to a plane of the polarized magnetic layer.
  10. Integrated chip according to Claim 8 or 9 , wherein the first BS electrode (104) has the polarized magnetic layer.
  11. Integrated chip according to one of the preceding Claims 8 until 10 , wherein: the MTJ device (109) has a free layer and a fixed layer; and the polarized magnetic layer is configured to have a magnetic field effective in reducing the number of precession cycles that the free layer of the MTJ device (109) undergoes during switching.
  12. Method for forming an integrated chip, comprising: forming an MTJ device (109) over a semiconductor substrate (302), wherein the MTJ device (109) has an MTJ arranged between a first electrode (105, 108) and a second electrode (105, 108); and forming a bipolar selector switch (101) for the MTJ device (109); wherein the bipolar selector switch (101) has a layer of ferromagnetic material with fixed polarization and the bipolar selector switch (101) is coupled to the second electrode (105, 108), wherein: the bipolar selector switch, BS, (101) has a non-metal layer or several non-metal layers (103) arranged between a first BS electrode (104) and a second BS electrode (102), and the formation of the bipolar selector switch (101) comprises oxidizing a section of the layer of ferromagnetic material to form the one non-metal layer or one (103b) of the several non-metal layers (103).
  13. Procedure according to Claim 12 , wherein the bipolar selector switch (101) is formed directly above or below the MTJ component (109).
  14. Procedure according to Claim 12 or 13 , wherein the MTJ device (109) has a fixed layer with a polarization that is nearly orthogonal to the fixed polarization of the layer of ferromagnetic material.

Description

GENERAL STATE OF THE ART Many electronic components contain electronic memory designed for data storage. Electronic memory can be volatile or non-volatile. Volatile electronic memory uses electricity to maintain data, while non-volatile memory is capable of storing data without electricity. Magnetoresistive random-access memory (MRAM) is a type of non-volatile memory that has long been the subject of active interest. Prior art relating to the subject matter of the invention can be found, for example, in US 2018 / 0 122 825 A1 , US 2018 / 0 240 845 A1 , US 2012 / 0 280 339 A1 , US 2014 / 0 301136 A1 , US 2009 / 0 027 976 A1 and DE 10 2019 127 079 A1 . The invention provides for an integrated chip according to claim 1, an integrated chip according to claim 8, and a method according to claim 12. Embodiments are specified in the dependent claims. BRIEF DESCRIPTION OF THE DRAWINGS Aspects of this disclosure are best understood with reference to the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with industry practice, various features are not shown to scale. In fact, the dimensions of the various features may have been arbitrarily enlarged or reduced for the sake of clarity. 1 presents a schematic diagram of a memory circuit with memory cells, comprising a magnetic tunnel junction device (MTJ device) and an access selection device with a polarized magnetic layer, designed to substantially reduce the switching time for the MTJ device according to some embodiments of this disclosure. 2A shows a trace of a magnetic field alignment vector for the free layer of an MTJ device during switching. 2B shows another trace of a magnetic field alignment vector for the free layer of an MTJ device during switching, which, compared to 2A shows how an initial tilt angle reduces the number of precession cycles in a switching operation. The 3A-3D Figures 1 and 2 show cross-sectional views of some embodiments of integrated circuits according to this disclosure with memory cells comprising an MTJ device and an access selection device with a polarized magnetic layer designed to substantially reduce the switching time for the MTJ device. 4 represents a block diagram of a memory circuit comprising a memory array with multiple memory cells, each having an access selection device, comprising a bipolar selection switch. 5 presents a cross-sectional view according to some embodiments of an integrated chip with memory cells, which includes a magnetic tunnel junction (MTJ) device and an access selection device with a polarized magnetic layer designed to substantially reduce the switching time for the MTJ device. The 6-14 represent some embodiments of a method for forming an integrated chip with memory cells, comprising a magnetic tunnel junction (MTJ) device and an access selection device with a polarized magnetic layer designed to substantially reduce the switching time for the MTJ device. The 15-16 represent some further embodiments of a method for forming an integrated chip with memory cells, comprising a magnetic tunnel junction device (MTJ device) and an access selection device with a polarized magnetic layer designed to substantially reduce the switching time for the MTJ device. 17 presents a flowchart for some embodiments of a method for forming an integrated chip with memory cells comprising a magnetic tunnel junction (MTJ) device and an access selection device with a polarized magnetic layer designed to substantially reduce the switching time for the MTJ device. DETAILED DESCRIPTION The following disclosure provides many different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components and arrangements are given. The following are described for the sake of simplicity in this disclosure. For example, the formation of a first feature over or on a second feature in the following description may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features are formed between the first and second features such that the first and second features cannot be in direct contact. Furthermore, this disclosure may repeat reference numerals and/or letters in the various examples. This repetition serves the purpose of simplification and clarity and does not in itself imply any relationship between the various embodiments and/or configurations discussed. Furthermore, spatial terms such as "below," "below," "lower," "above," "upper," and the like, used herein for the sake of simplicity, may be used to describe the relationship of one element or feature to another element(s) or feature(s) as illustrated in the figures. These spatial terms are intended to encompass different orientations of the component during use or operation, in addition to the orientation shown in the figures. The device may be oriented differently (rotated by 9