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DE-102020115429-B4 - Amorphous layers for reducing copper diffusion and their manufacturing processes

DE102020115429B4DE 102020115429 B4DE102020115429 B4DE 102020115429B4DE-102020115429-B4

Abstract

Procedure comprehensive: Deposition of a cover layer (24) having a polycrystalline structure over a first conductive feature (22), wherein the cover layer (24) comprises cobalt nitride and has a thickness between about 2 nm and about 4 nm; Performing a treatment process to convert the polycrystalline structure of the cover layer (24) into an amorphous structure; Deposition of a first etch stop layer (30A) over the metal cover (24) with the amorphous structure; Performing an initial treatment (32) to amorphize the first etch stop layer (30A); Deposition of a dielectric layer (34) over the first etch stop layer (30A); Etching the dielectric layer (34) to form an opening; Etching through the first etch stop layer (30A) to enlarge the opening into the first etch stop layer (30A); and Filling the opening with a conductive material (42) to form a second conductive feature.

Inventors

  • Jyh-Nan Lin
  • Chia-Yu Wu
  • Kai-Shiung Hsu
  • Ding-l Liu

Assignees

  • TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Dates

Publication Date
20260513
Application Date
20200610
Priority Date
20200602

Claims (18)

  1. The method comprises: Depositing a cover layer (24) with a polycrystalline structure over a first conductive feature (22), wherein the cover layer (24) comprises cobalt nitride and has a thickness between about 2 nm and about 4 nm; Performing a treatment process to convert the polycrystalline structure of the cover layer (24) into an amorphous structure; Depositing a first etch stop layer (30A) over the metal cover (24) with the amorphous structure; Performing a first treatment (32) to amorphize the first etch stop layer (30A); Depositing a dielectric layer (34) over the first etch stop layer (30A); Etching the dielectric layer (34) to form an opening; Etching through the first etch stop layer (30A) to enlarge the opening into the first etch stop layer (30A); and filling the opening with a conductive material (42) to form a second conductive feature.
  2. Procedure according to Claim 1 , wherein the first treatment (32) comprises bombarding the first etch stop layer (30A) using a process gas containing ammonia (NH 3 ).
  3. Procedure according to Claim 1 or 2 , wherein the first treatment (30A) is performed using a low-frequency radio frequency power in a range between approximately 90 watts and approximately 135 watts.
  4. Method according to one of the preceding claims, wherein the deposition of the first etch stop layer (30A) is carried out at a temperature in a range between about 300 °C and about 380 °C.
  5. A method according to any one of the preceding claims, further comprising: prior to the deposition of the first etch stop layer and the formation of the amorphous metal cover (24), performing a further treatment process on the first conductive feature to form a copper nitride on the first conductive feature; depositing cobalt onto the copper nitride; converting the copper nitride into the cover layer (24) comprising cobalt nitride.
  6. Procedure according to Claim 1 , wherein the formation of the amorphous metal cover (24) comprises: depositing a metal cover (24); and after depositing the metal cover (24), bombarding the metal cover (24) to create amorphous structures in the metal cover (24).
  7. A method according to any of the preceding claims, further comprising: after forming the second conductive feature, carrying out a high-temperature process, wherein the first etch stop layer (30A) is transformed to have polycrystalline structures.
  8. A method according to any of the preceding claims, further comprising: depositing a second etch stop layer (30B) over the first etch stop layer (30A); and depositing a third etch stop layer (30C) over the second etch stop layer (30B), wherein the dielectric layer (34) is formed over the third etch stop layer (30C), the opening extending further through the third etch stop layer (30C) and the second etch stop layer (30B).
  9. comprising an integrated circuit structure: a first dielectric layer (16); a first conductive feature (22) extending into the first dielectric layer (16); an amorphous metal cover (24) over and in contact with the first conductive feature (22), wherein the amorphous metal cover (24) comprises cobalt nitride and has a thickness between about 2 nm and about 4 nm; an amorphous first etch stop layer (30A) over the metal cover (24); a low-k dielectric layer (34) over the amorphous first etch stop layer (30A); and a second conductive feature extending into the low-k dielectric layer (34) and the amorphous first etch stop layer (30A).
  10. Integrated circuit structure according to Claim 9 , wherein the amorphous first etch stop layer (30A) comprises an amorphous aluminium nitride layer.
  11. Integrated circuit structure according to Claim 10 , wherein the amorphous aluminium nitride layer contains hydrogen.
  12. Integrated circuit structure according to one of the Claims 9 until 11 , wherein the amorphous first etch stop layer (30A) contacts the metal cover (24).
  13. Integrated circuit structure according to Claim 11 , wherein the aluminium nitride layer has a hydrogen atom percentage in the range of 1 percent to 3 percent.
  14. Integrated circuit structure according to one of the Claims 9 until 13 , further comprising: a second etch stop layer (30B) over the amorphous first etch stop layer (30A); and a third etch stop layer (30C) over the second etch stop layer (30B), wherein the second conductive feature penetrates through the second etch stop layer (30B) and the third etch stop layer (30C) to contact the metal cover (24).
  15. The integrated circuit structure comprises: a first low-k dielectric layer (16); a first conductive feature (22) extending into the first low-k dielectric layer (16), the first conductive feature (22) containing copper; an amorphous metal cover (24) over and in contact with the first conductive feature (22), the amorphous metal cover (24) comprising cobalt nitride and having a thickness between about 2 nm and about 4 nm; and an etch stop layer (30A-C) comprising: - an amorphous aluminum nitride layer over and in contact with the metal cover (24) and the first low-k dielectric layer (16), the amorphous aluminum nitride layer forming a first sub-etch stop layer; - a second sub-etch stop layer over the first sub-etch stop layer; and - a third sub-etch stop layer over the second sub-etch stop layer; a second low-k dielectric layer (34) over the third sub-etch stop layer; and a conductive via (44) extending into the second low-k dielectric layer (34) and the etch stop layer (30A-C).
  16. Integrated circuit structure according to Claim 15 , wherein the aluminium nitride layer has a hydrogen atom percentage in the range of 1 percent to 3 percent.
  17. Integrated circuit according to Claim 15 or 16 , wherein the metal cover (24) has a thickness in the range of about 2 nm and about 4 nm.
  18. Integrated circuit structure according to one of the Claims 15 until 17 , wherein the second sub-etch stop layer contains silicon dioxide and the third sub-etch stop layer contains aluminum oxide.

Description

TECHNICAL BACKGROUND High-density integrated circuits, such as very large-scale integration (VLSI) circuits, are typically formed with multiple metal connections to serve as three-dimensional wiring structures. The purpose of these multiple connections is to ensure the proper interconnection of densely packed devices. As the level of integration increases, parasitic capacitance between the metal connections becomes more pronounced, leading to RC delay and crosstalk. To reduce parasitic capacitance and increase the conduction velocity between the metal connections, dielectrics with low k-values are commonly used to form interlayer dielectric (ILD) and intermetal dielectric (IMD) layers. Metal conductors and vias are formed within the IMD layers. A formation process can involve forming an etch stop layer over initial conductive features and a low-k dielectric layer over the etch stop layer. The low-k dielectric layer and the etch stop layer are structured to form a trench and via opening. The trench and via opening are then filled with a conductive material, followed by a planarization process to remove excess conductive material, thus forming a metal conductor and via. US 2017 / 0 278 742 A1 discloses a method for producing a heterostructure. JP H05- 291 560 A reveals a barrier metal that can exhibit higher barrier properties, even when the film is thin. US 2016 / 0 197 136 A1 discloses semiconductor devices and methods for their manufacture. BRIEF DESCRIPTION OF THE DRAWINGS Aspects of this disclosure are best understood with reference to the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with industry practice, various features are not shown to scale. In fact, the dimensions of the various features may have been arbitrarily enlarged or reduced for the sake of clarity. 1 to 12 The cross-sectional views of the intermediate stages in the formation of the connection structure according to some embodiments are illustrated. 13 illustrates an exemplary profile of a section of a connection structure according to some embodiments. 14 illustrates the process flow for forming the connection structure according to some embodiments. DETAILED DESCRIPTION The invention is defined by claims 1, 9, and 15, which define a method, an integrated circuit structure, and an integrated circuit design. Embodiments of the invention are given in the dependent claims, the description, and the drawings. The following disclosure provides many different embodiments or examples of the implementation of various features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. For example, forming a first feature or a second feature in the following description may include embodiments in which the first and second features are formed in direct contact, and it may also include embodiments in which further features can be formed between the first and second features, such that the first and second features do not have to be in direct contact. Furthermore, this disclosure may repeat reference numbers and/or letters of the various examples. This repetition is for the sake of simplicity and clarity and does not, in itself, dictate a relationship between the various embodiments and/or configurations described. Furthermore, spatially relative terms such as "underlying," "below," "lower," "above," "upper," and the like may be used herein for the sake of simplicity to describe the relationship of one element or feature to one or more other elements or features, as illustrated in the drawings. These spatially relative terms are intended to encompass various orientations of the device in use or operation, in addition to the orientation shown in the drawings. The device may be oriented differently (rotated by 90 degrees or in another orientation), and the spatially relative terms used herein may be interpreted accordingly. A compound structure and the method for forming it are provided according to some embodiments. The intermediate steps in forming the compound structure are illustrated according to some embodiments. Some variations of some embodiments are described. The embodiments described herein are intended to provide examples for producing or using the content of this disclosure, and a person with ordinary skills in the field will readily understand modifications that may be made without departing from the considered scopes of various embodiments. In the various views and illustrative embodiments, the same reference numerals are used to denote the same elements. Although some embodiments of the process may be declared herein to be carried out in a particular order, other embodiments may be carried out in any logical order. According to some embodiments of this disclosure, forming a compound structure includes depositing a metal cover over the first conductive feature, performing a first treatment to amorphize th