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DE-102020119609-B4 - NEW GATE STRUCTURES FOR SETTING THE LIMIT VOLTAGE AND METHOD

DE102020119609B4DE 102020119609 B4DE102020119609 B4DE 102020119609B4DE-102020119609-B4

Abstract

Device comprising: a substrate (110); an interface layer (210) formed above the substrate (110), wherein the interface layer (210) has a dipole-penetrated section (210A); a gate dielectric layer (430) formed above the interface layer (210); and a metal gate electrode formed above the gate dielectric layer (430), wherein the dipole-penetrated section (210A) comprises yttrium oxide Y 2 O 3 , niobium oxide Nb 2 O 5 , titanium oxide TiO 5 , boron oxide B 2 O 3 , phosphorus pentoxide P 2 O 5 or phosphorus trioxide P 2 O 3 .

Inventors

  • Yen-Yu Chen
  • Chung-Liang Cheng

Assignees

  • TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Dates

Publication Date
20260513
Application Date
20200724
Priority Date
20200710

Claims (20)

  1. Device comprising: a substrate (110); an interface layer (210) formed over the substrate (110), wherein the interface layer (210) has a dipole-penetrated section (210A); a gate dielectric layer (430) formed over the interface layer (210); and a metal gate electrode formed over the gate dielectric layer (430), wherein the dipole-penetrated section (210A) comprises yttrium oxide Y₂O₃, niobium oxide Nb₂O₅, titanium oxide TiO₅, boron oxide B₂O₃ , phosphorus pentoxide P₂O₅ , or phosphorus trioxide P₂O₃ .
  2. Device according to Claim 1 , wherein a maximum concentration of a dipole material within the dipole-penetrated section (210A) decreases as the distance from an upper surface of the dipole-penetrated section (210A) increases.
  3. Device according to Claim 1 or 2 , wherein a lower section of the gate dielectric layer (430) comprises a dipole material that has diffused from the interface layer (210).
  4. Device according to one of the preceding claims, wherein: the metal gate electrode comprises an exit work metal component and a filler metal component formed above the exit work metal component; and the exit work metal component comprises an exit work metal layer (620) which is inserted between a first protective layer (610) and a second protective layer (630).
  5. Device according to Claim 4 , wherein the exit working metal layer (620) comprises TiAlC and wherein the first protective layer (610) and the second protective layer (630) each comprise TiN.
  6. Device according to one of the preceding claims, wherein the device comprises a FinFET device or a gate all-around device.
  7. Device comprising: a first gate structure (200) comprising a first interface layer (210), a first gate dielectric layer (430) arranged above the first interface layer (210), and a first gate electrode arranged above the first gate dielectric layer (430); and a second gate structure (200) comprising a second interface layer (210), a second gate dielectric layer (430) arranged above the second interface layer (210), and a second gate electrode arranged above the second gate dielectric layer (430); wherein the first interface layer (210) comprises a different amount of a dipole material than the second interface layer (210), wherein the dipole material comprises yttrium oxide Y 2 O 3 , niobium oxide Nb 2 O 5 , titanium oxide TiO 5 , boron oxide B 2 O 3 , phosphorus pentoxide P 2 O 5 or phosphorus trioxide P 2 O 3 .
  8. Device according to Claim 7 , wherein: a peak concentration of the dipole material in the first interface layer (210) occurs at an interface between the first interface layer (210) and the first gate dielectric layer (430); or a peak concentration of the dipole material in the second interface layer (210) occurs at an interface between the second interface layer (210) and the second gate dielectric layer (430).
  9. Device according to Claim 7 or 8 , wherein: a first section (210A) of the first interfacial layer (210) comprises the dipole material, wherein the first section (210A) has a first depth or a first dipole concentration plane; and a second section (210A) of the second interfacial layer (210) comprises the dipole material, wherein the second section (210A) has a second depth different from the first depth or a second concentration plane different from the first dipole concentration plane.
  10. device according to one of the preceding Claims 7 until 9 , wherein: the first gate structure (200) is associated with a first limiting voltage; and the second gate structure (200) is associated with a second limiting voltage which differs from the first limiting voltage.
  11. device according to one of the preceding Claims 7 until 10 , wherein the dipole material is a first dipole material and wherein the device further comprises: a third gate structure (200) comprising a third interface layer (210), a third gate dielectric layer (430) arranged above the third interface layer (210), and a third gate electrode arranged above the third gate dielectric layer (430); and a fourth gate structure (200) comprising a fourth interface layer (210), a fourth gate dielectric layer (430) arranged above the fourth interface layer (210), and a fourth gate electrode arranged above the fourth gate dielectric layer (430); wherein: the third interface layer (210) comprises a different quantity of a second dipole material than the fourth interface layer (210); the first gate structure (200) and the second gate structure (200) are components of N-transistors; and the third gate structure (200) and the fourth gate structure (200) are components of P-transistors.
  12. Device according to Claim 11 , where the first dipole material and the second dipole material are both N-dipole materials or both P-dipole materials.
  13. Device according to Claim 11 , where: the first dipole material comprises an N-dipole material; and the second dipole material comprises a P-dipole material.
  14. Method comprising: forming a mask layer (230, 260) over a first interface layer, IL, (210) for a first gate structure (200) and over a second IL (210) for a second gate structure (200); structuring the mask layer (230, 260) to remove a section of the mask layer (230, 260) formed over the first IL (210); forming a dipole layer (300), wherein a first section of the dipole layer (300) is formed directly on the first IL (210) and wherein a second section of the dipole layer (300) is formed on a remaining section of the mask layer (230, 260) arranged over the second IL (210); and carrying out a dipole insertion process (350) to insert a material of the dipole layer (300) into the first IL (210) and the second IL (210), wherein the dipole layer (300) comprises yttrium oxide Y 2 O 3 , niobium oxide Nb 2 O 5 , titanium oxide TiO 5 , boron oxide B 2 O 3 , phosphorus pentoxide P 2 O 5 or phosphorus trioxide P 2 O 3 .
  15. Procedures from Claim 14 , wherein: the dipole insertion process (350) forms a first dipole-penetrated section (210A) in the first IL (210) and a second dipole-penetrated section (210A) in the second IL (210); the first dipole-penetrated section (210A) has a first depth; the second dipole-penetrated section (210A) has a second depth; and the first depth is greater than the second depth.
  16. Procedure according to Claim 14 or 15 , wherein after the execution of the dipole insertion process (350): the first IL (210) has a first concentration value of the material of the dipole layer (300); the second IL (210) has a second concentration value of the material of the dipole layer (300); and the first concentration value is greater than the second concentration value.
  17. procedure according to one of the preceding Claims 14 until 16 , wherein the dipole insertion process (350) includes a tempering process which is carried out in a temperature range between approximately 600 degrees Celsius and 800 degrees Celsius and with a nitrogen gas.
  18. procedure according to one of the preceding Claims 14 until 17 , further comprising: removal of the dipole layer (300) and removal of the remaining section of the mask layer (230, 260) after performing the dipole insertion process (350); forming a gate dielectric layer (430) directly on the first IL (210) and the second IL (210); forming one or more exit work metals layers (530, 620, 780, 860) over the gate dielectric layer (430); and forming a filler metal (690) over the one or more exit work metal layers (530, 620, 780, 860).
  19. Procedure according to Claim 18 , wherein the formation of one or more exit work metal layers (530, 620, 780, 860) comprises: forming a first exit work metal layer (530, 620, 780, 860) over the gate dielectric layer (430); forming a second exit work metal layer (530, 620, 780, 860) over the first exit work metal layer (530, 620, 780, 860); and forming a third exit work metal layer (530, 620, 780, 860) over the second exit work metal layer (530, 620, 780, 860); wherein: the first exit metal layer (530, 620, 780, 860) and the third exit metal layer (530, 620, 780, 860) have the same material compositions; and the second exit metal layer (530, 620, 780, 860) has a different material composition than the first exit metal layer (530, 620, 780, 860) and the third exit metal layer (530, 620, 780, 860).
  20. Procedure according to Claim 19 , wherein the first exit work metal layer (530, 620, 780, 860), the second exit work metal layer (530, 620, 780, 860) and the third exit work metal layer (530, 620, 780, 860) are formed in situ using the same deposition tool.

Description

BACKGROUND The semiconductor integrated circuit (IC) industry has grown exponentially. Technological advances in IC materials and design have produced generations of ICs, each generation featuring smaller and more complex circuitry than the previous one. As ICs have evolved, functional density (i.e., the number of connected devices per chip area) has generally increased, while geometric size (i.e., the smallest component (or trace) that can be produced using a manufacturing process) has decreased. This scale-down process generally offers benefits by increasing production efficiency and reducing associated costs. However, this scale-down has also increased the complexity of IC processing and manufacturing. For example, the limiting voltage in conventional devices can be adjusted by increasing the thickness of different exit metals of a gate electrode. However, with ongoing downscaling, increasing the thickness of these different exit metals becomes impractical and/or can lead to various manufacturing problems. Therefore, while conventional methods for determining the limit voltages are generally appropriate, they are not satisfactory in all aspects. Printed matter US 2014 / 0 264 626 A1 This describes gate structures with a dielectric base layer, a dielectric layer, a cover layer, and an electrode material over a substrate. A metallic layer containing lanthanum or aluminum is applied, which diffuses into the dielectric layers during a tempering process. document US 2015 / 0 104 933 A1 describes the formation of dipoles between two dielectric layers of a gate structure. document US 2012 / 0 049 297 A1 This describes a gate structure with dielectric layers and a gate electrode consisting of metallic layers. Different lanthanum concentration distributions are found in the dielectric layers. document US 2015 / 0 035 073 A1 describes gate structures with dielectric layers. document US 2019 / 0 318 967 A1 This describes gate structures with a dielectric boundary layer, a gate dielectric layer, a blocking layer, and a superimposed dipole layer. Dipole doping is driven from the dipole layer into the gate dielectric layer using a annealing process. document US 2011 / 0 127 616 A1 describes the manufacturing of gate structures. document DE 11 2011 101 277 B4 describes the manufacturing of gate structures. The invention is defined by the main claim and the dependent claims. Further embodiments of the invention are described by the dependent claims. BRIEF DESCRIPTION OF THE DRAWINGS The following detailed description is best understood with the help of the accompanying drawings. It should be noted that, according to industry standard practice, various features are not drawn to scale and are for illustrative purposes only. In fact, the dimensions of the various features may have been arbitrarily enlarged or reduced for the sake of clarity. 1A This is a perspective view of an IC device according to various aspects of this revelation. 1B This is a top view of an IC device according to various aspects of this revelation. 2A to 21A, 2B to 21B, 2C to 21C, 2D to 21D, 2E to 21E and 2F to 21F and 22 to 23 These are cross-sectional views of different embodiments of an IC device at different stages of manufacture according to different aspects of this disclosure. 24 is a flowchart illustrating a process for manufacturing a semiconductor device according to various aspects of this disclosure. DETAILED DESCRIPTION The following disclosure provides many different embodiments or examples of the implementation of various features of the disclosure. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, only examples and are not to be understood as limiting. For example, The formation of a first feature or a second feature in the following description includes embodiments in which the first and second features are formed in direct contact, and it may also include embodiments in which further features can be formed between the first and second features, so that the first and second features need not be in direct contact. Furthermore, this disclosure may repeat reference numbers and/or letters of the various examples. This repetition is for the sake of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations described. Furthermore, this disclosure may repeat reference numbers and/or letters from the various examples. This repetition serves for simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations described. Furthermore, the formation of a feature on, connected with, and/or coupled to another feature in this subsequent disclosure may include embodiments in which the features are formed in direct contact, and may also include embodiments in which further features can be formed between the features, so that the features need not be in dir