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DE-102020120658-B4 - Transistor gates and methods for their manufacture

DE102020120658B4DE 102020120658 B4DE102020120658 B4DE 102020120658B4DE-102020120658-B4

Abstract

Device with: a first nanostructure (52A); a second nanostructure (52B) above the first nanostructure (52A); a first high-k gated dielectric (103) arranged around the first nanostructure (52A); a second high-k gated dielectric (103A) arranged around the second nanostructure (52B); and a gate electrode (102), above the first high-k gate dielectric (103) and the second high-k gate dielectric (103A), wherein a part of the gate electrode (102) between the first nanostructure (52A) and the second nanostructure (52B) has a first part of a p-exit work metal (105), wherein the first part of the p-exit work metal (105) fills an entire region between the first high-k gate dielectric (103) and the second high-k gate dielectric, and wherein the first part of the p-exit work metal (105) consists throughout of the same material, and wherein the first part of the p-exit work metal (105) has a first thickness (T2) and a second part of the p-exit work metal (105) on a side wall of the first nanostructure (52A) has a second thickness (T1), wherein the first thickness (T2) is greater than the second thickness (T1).

Inventors

  • Hsin-Yi Lee
  • Ji-Cheng Chen
  • Cheng-Lung Hung
  • Chi On Chui

Assignees

  • TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Dates

Publication Date
20260513
Application Date
20200805
Priority Date
20200730

Claims (20)

  1. Device comprising: a first nanostructure (52A); a second nanostructure (52B) above the first nanostructure (52A); a first high-k gated dielectric (103) arranged around the first nanostructure (52A); a second high-k gated dielectric (103A) arranged around the second nanostructure (52B); and a gate electrode (102), above the first high-k gate dielectric (103) and the second high-k gate dielectric (103A), wherein a portion of the gate electrode (102) between the first nanostructure (52A) and the second nanostructure (52B) comprises a first portion of a p-exit work metal (105), wherein the first portion of the p-exit work metal (105) fills an entire region between the first high-k gate dielectric (103) and the second high-k gate dielectric, and wherein the first portion of the p-exit work metal (105) is composed entirely of the same material, and in which the first portion of the p-exit work metal (105) has a first thickness (T2) and a second portion of the p-exit work metal (105) on a side wall of the first nanostructure (52A) has a second thickness (T1) has, where the first thickness (T2) is greater than the second thickness (T1).
  2. Device according to Claim 1 , wherein the first part of the p-exit work metal (105) has a seam (105S) between the first and the second nanostructure (52A, 52B).
  3. Device according to Claim 1 or 2 , wherein the p-exit work metal (105) comprises titanium nitride.
  4. Device according to Claim 3 , where the ratio of the first thickness (T 2 ) to the second thickness (T1) is not greater than 2 : 1.
  5. Device according to Claim 3 or 4 , where the second thickness (T1) is 3 nm to 5 nm.
  6. device according to one of the Claims 3 until 5 , wherein the ratio of the second thickness (T1) to a minimum width (W2) of the p-exit working metal (105) is 0.03 to 1.
  7. Device according to Claim 6 , wherein the minimum width (W 2 ) of the p-exit work metal (105) is 10 nm to 180 nm.
  8. Device according to one of the preceding claims, wherein the part of the gate electrode (102) between the first high-k-gate dielectric (103) and the second high-k-gate dielectric (103A) has no barrier layers.
  9. Device according to one of the preceding claims, wherein the gate electrode (102) further comprises an adhesive layer (115) over the p-exit work metal (105), wherein the adhesive layer (115) does not extend between the first nanostructure (52A) and the second nanostructure (52B).
  10. Device according to one of the preceding claims, wherein the ratio of a height (H1) of the first nanostructure (52A) to a width (W1) of the first nanostructure (52A) is 0.05 to 4.
  11. Transistor comprising: a first nanostructure (52A) over a semiconductor substrate (50); a second nanostructure (52B) over the first nanostructure (52A); a gate dielectric (103) enclosing the first nanostructure (52A) and the second nanostructure (52B); and a gate electrode (102) above the gate dielectric (103), wherein the gate electrode (102) comprises: a p-type work-source metal (105), wherein the p-type work-source metal (105) extends continuously from a first part of the gate dielectric (103) on the first nanostructure (52A) to a second part of the gate dielectric (103) on the second nanostructure (52B), wherein the p-type work-source metal (105) fills an entire region between the first part of the gate dielectric (103) and the second part of the gate dielectric (103), and wherein the p-type work-source metal (105) is composed of the same material throughout, and wherein the p-type work-source metal (105) has a first thickness (T1) on a top side of the second nanostructure and a second thickness (T2) between the first nanostructure and the second nanostructure, wherein the first thickness (T1) is smaller than the second thickness (T2); and a bonding layer (115) over the p-exit work metal (105), and a filler metal (117) over the bonding layer (115).
  12. transistor after Claim 11 , where the ratio of the second thickness (T2) to the first thickness (T1) is not greater than 2 : 1.
  13. transistor after Claim 11 or 12 , wherein the p-exit work metal (105) has a seam (105S) between the first nanostructure (52A) and the second nanostructure (52B).
  14. transistor after one of the Claims 11 until 13 , wherein the p-exit work metal (105) comprises titanium nitride.
  15. transistor after one of the Claims 11 until 14 , which further comprises an interface layer (101) beneath the gate dielectric (103), wherein the interface layer (101) encloses the first nanostructure (52A) and the second nanostructure (52B) and the gate dielectric (103) comprises a high-k material.
  16. Method comprising the following steps: Deposition of a gate dielectric (103) around a first nanostructure (52A) and a second nanostructure (52B), wherein the first nanostructure (52A) is arranged over the second nanostructure (52B); and depositing a p-type exit work metal (105) over the gate dielectric (103), wherein the deposition of the p-type exit work metal (105) comprises: depositing a first part of the p-type exit work metal (105) on a top surface of the second nanostructure (52B) and a second part of the p-type exit work metal (105) on a bottom surface of the first nanostructure (52A), and continuing the deposition of the p-type exit work metal (105) until the first part of the p-type exit work metal (105) merges with the second part of the p-type exit work metal (105), wherein the p-type exit work metal (105) fills an entire region between the gate dielectric (103) around the first nanostructure and the gate dielectric (103) around the second nanostructure, and the p-type exit work metal consists of the same material throughout, whereby the deposition of the p-exit work metal (105) comprises a deposition of the p-exit work metal (105) such that it has a first thickness (T2) between the first nanostructure and the second nanostructure, and a second thickness (T1) on a side wall of the first nanostructure, wherein the first thickness (T2) is greater than the second thickness (T1).
  17. Procedure according to Claim 16 , which further comprises: depositing an adhesive layer (115) over the p-exit work metal (105); and depositing a filler metal (117) over the adhesive layer (115).
  18. Procedure according to Claim 16 or 17 , wherein the p-exit work metal (105) comprises titanium nitride.
  19. Procedure according to Claim 18 , where the ratio of the first thickness (T2) to the second thickness (T1) is not greater than 2 : 1.
  20. Procedure according to one of the Claims 16 until 19 , wherein the deposition of the p-exit work metal (105) comprises forming a seam (105S) between the first part of the p-exit work metal (105) and the second part of the p-exit work metal (105).

Description

background Semiconductor devices are used in various electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by successively depositing insulating or dielectric material layers, conductive material layers, and semiconductor material layers onto a semiconductor substrate. The different material layers are then structured by lithography to create circuit components and elements on the substrate. The semiconductor industry is constantly improving the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continuously reducing the smallest feature size, thus enabling the integration of more components in a given area. However, reducing the smallest feature size introduces further problems that need to be addressed. The US 9997519 B1 Disclosing a semiconductor device with a gate stack, wherein the gate stack comprises multiple nanostructures and wherein a barrier layer is arranged around each nanostructure. US 2020 / 0 119 167 A1 A gate all-round transistor (GAA) with horizontal nanostructures made from a multilayer structure with improved etch selectivity is revealed. US 2020 / 0 083 327 A1 discloses a semiconductor device with a first nanostructure and a second nanostructure, each having corresponding source/drain structures and contacts, wherein a lower part of the first contact is lower than a bottom section of the first nanostructure and a lower part of the second contact is higher than an upper section of the second nanostructure. Brief description of the drawings Aspects of the present invention are best understood with reference to the detailed description below in conjunction with the accompanying drawings. It should be noted that, in accordance with common industry practice, various elements are not drawn to scale. Rather, for the sake of clarity of discussion, the dimensions of the various elements may be arbitrarily enlarged or reduced. 1 shows an example of a nanostructured field-effect transistor (nano-FET) according to some embodiments in a three-dimensional representation. The 2 , 3 , 4 , 5 , 6A , 6B , 7A , 7B Figures 8A, 8B, 9A, 9B, 10A, 10B, 11A, 11B, 11C, 12A, 12B, 12C, 12D, 13A, 13B, 13C, 14A, 14B, 15A, 15B, 16A, 16B, 17A, 17B, 18A, 18B, 19A, 19B, 19C, 19D, 22A, 22B, 23A, 23B, 23C, 24A, 24B, 24C, 25A, 25B and 25C are sectional and top views of intermediate stages in the fabrication of nano-FETs according to some embodiments. 20 This is a sectional view of a nano-FET according to some embodiments. 21 This is a sectional view of a nano-FET according to some embodiments. The 26A , 26B and 26C These are sectional views of a nano-FET according to some embodiments. Detailed description The following description provides many different embodiments or examples for implementing various features of the invention. Specific examples of components and arrangements are described below to simplify the present invention. These are, of course, merely examples and are not intended to be limiting. For example, the fabrication of a first element above or on top of a second element in the following description may include embodiments in which the first and second elements are fabricated in direct contact, and it may also include embodiments in which additional elements can be fabricated between the first and second elements, such that the first and second elements are not in direct contact. Furthermore, reference numerals and/or letters may be repeated in the various examples in the present invention. This repetition serves for simplicity and clarity and does not, in itself, prescribe a relationship between the various embodiments and/or configurations discussed. Furthermore, spatially relative terms, such as "located below,""under,""lower,""locatedabove,""upper," and the like, can be used here to simply describe the relationship of an element or structure to one or more other elements or structures depicted in the figures. These spatially relative terms should encompass orientations of the device in use or operation in addition to the orientation shown in the figures. The device may be oriented differently (rotated by 90 degrees or in a different orientation). orientation), and the spatially relative descriptors used here can be interpreted accordingly. In transistor gate stacks, the thickness of one or more exit work metal (WFM) layers influences the transistor's threshold voltage (V<sub>TH</sub> ). However, it has been found that thickness variations due to fused areas of the WFM layers (e.g., between nanowires of a nanoFET) do not significantly affect the transistor's electrical properties. Furthermore, by omitting a depletion layer around the WFM layer (to prevent, for example, fusion of parts of the WFM layer), fabrication can be simplified. This is particularly relevant for modern semiconductor nodes with small feature sizes, as depletion laye