Search

DE-102020126167-B4 - Field effect transmitters with channel areas comprising a two-dimensional material, on a mandrel, and methods for forming these field effect transmitters

DE102020126167B4DE 102020126167 B4DE102020126167 B4DE 102020126167B4DE-102020126167-B4

Abstract

Structure for a field-effect transistor, wherein the structure comprises: a first mandrel (38, 56) composed of a dielectric material, wherein the first mandrel (38, 56) comprises a plurality of side surfaces (39, 59), the plurality of side surfaces (39, 59) comprising a first side surface and a second side surface; a second mandrel (38, 56) composed of the dielectric material, wherein the second mandrel (38, 56) comprises a side surface, and the second mandrel (38, 56) is arranged above the first mandrel (38, 56); a gate electrode having a section (43) that is enveloped around the first side surface and the second side surface of the first mandrel (38, 56); a first channel layer (34) comprising a channel region (70), wherein the channel region (70) of the first channel layer (34) extends around all of the side surfaces (39, 59) of the first mandrel (38, 56) and is positioned partly between the first side surface of the first mandrel (38, 56) and the section (43) of the gate electrode and partly between the second side surface of the first mandrel (38, 56) and the section (43) of the gate electrode; and a second channel layer (34) comprising a channel region (70) that is partially positioned between the side surface of the second mandrel (38, 56) and the section (43) of the gate electrode, wherein the first channel layer (34) and the second channel layer (34) are composed of a two-dimensional material.

Inventors

  • Julien Frougier

Assignees

  • GLOBALFOUNDRIES U.S. INC.

Dates

Publication Date
20260513
Application Date
20201007
Priority Date
20191030

Claims (17)

  1. Structure for a field-effect transistor, the structure comprising: a first mandrel (38, 56) composed of a dielectric material, wherein the first mandrel (38, 56) comprises a plurality of side surfaces (39, 59), the plurality of side surfaces (39, 59) comprising a first side surface and a second side surface; a second mandrel (38, 56) composed of the dielectric material, wherein the second mandrel (38, 56) comprises a side surface, and the second mandrel (38, 56) is arranged above the first mandrel (38, 56); a gate electrode having a section (43) that surrounds the first side surface and the second side surface of the first mandrel (38, 56); a first channel layer (34) comprising a channel region (70), wherein the channel region (70) of the first channel layer (34) extends around all of the side surfaces (39, 59) of the first mandrel (38, 56) and is partially positioned between the first side surface of the first mandrel (38, 56) and the section (43) of the gate electrode and partially between the second side surface of the first mandrel (38, 56) and the section (43) of the gate electrode; and a second channel layer (34) comprising a channel region (70) that is partially positioned between the side surface of the second mandrel (38, 56) and the section (43) of the gate electrode, in which the first channel layer (34) and the second channel layer (34) are composed of a two-dimensional material.
  2. Structure according to Claim 1 , where the first side surface and the second side surface of the first mandrel (38, 56) are contained in respective planes which are essentially parallel.
  3. Structure according to Claim 1 or Claim 2 , wherein the first channel layer (34) comprises an extension area (72), the second channel layer (34) comprises an extension area (72), and further comprising: a source/drain contact (40) which is connected to the channel area (70) of the first channel layer (34) by the extension area (72) of the first channel layer (34) and which is connected to the channel area (70) of the second channel layer (34) by the extension area (72) of the second channel layer (34).
  4. Structure according to Claim 3 , wherein the first mandrel (38, 56) and the second mandrel (38, 56) each terminate at the source/drain contact (40) in direct contact with the source/drain contact (40), the extension area (72) of the first channel layer (34) extends completely around the first mandrel (38, 56), and the extension area (72) of the second channel layer (34) extends completely around the second mandrel (38, 56).
  5. Structure according to Claim 4 , further comprising: an inner spacer (30) positioned in a first direction between the section (43) of the gate electrode and the source/drain contact (40), wherein the inner spacer (30) is positioned in a second direction between the extension area (72) of the first channel layer (34) and the extension area (72) of the second channel layer (34).
  6. Structure according to Claim 1 , wherein the first channel layer (34) comprises a first extension area (72), and further comprising: a first source/drain contact (40) which is connected to the channel area (70) of the first channel layer (34) by the first extension area (72) of the first channel layer (34).
  7. Structure according to Claim 6 , wherein the first channel layer (34) comprises a second extension area (72), the channel area (70) of the first channel layer (34) is positioned between the first extension area (72) and the second extension area (72) of the first channel layer (34), and further comprising: a second source/drain contact (40) which is connected to the channel area (70) of the first channel layer (34) through the second extension area (72) of the first channel layer (34).
  8. Structure according to Claim 7 , wherein the channel area (70), the first extension area (72) and the second extension area (72) of the first channel layer (34) extend around all of the side surfaces (39, 59) of the first mandrel (38, 56).
  9. Structure according to Claim 6 , further comprising: a layer (36) of the two-dimensional material that couples the first extension area (72) of the first channel layer (34) with the first source/drain contact (40).
  10. Structure according to Claim 9 , wherein the layer (36) of the two-dimensional material contains a dopant that is effective in increasing the electrical conductivity of the two-dimensional material.
  11. Structure according to Claim 6 , further comprising: a first inner spacer (30) and a second inner spacer (30) positioned in a first direction between the section (43) of the gate electrode and the first source/drain contact (40), wherein the first extension area (72) is positioned in a second direction between the first inner spacer (30) and the second inner spacer (30), and the first mandrel (38, 56) terminates at the first inner spacer (30) and the second inner spacer (30).
  12. Structure according to one of the Claims 1 until 11 , where the two-dimensional material is a transition metal dichalcogenide.
  13. Structure according to one of the Claims 1 until 12 , where the two-dimensional material is molybdenum disulfide, hafnium disulfide, zirconium disulfide, tungsten disulfide, tin sulfide, or tungsten diselenide.
  14. Method for forming a field-effect transistor, the method comprising: forming a first channel layer (34) and a second channel layer (34), both channel layers (34) comprising a channel region (70); forming a first dielectric mandrel (38, 56) comprising a plurality of side surfaces (39, 59); forming a second dielectric mandrel (38, 56) comprising a side surface and arranged above the first dielectric mandrel (38, 56); and forming a gate electrode having a section (43) enclosed around a first side surface and a second side surface of the plurality of side surfaces (39, 59) of the first dielectric mandrel (38, 56); wherein the channel area (70) of the first channel layer (34) extends around all of the side surfaces (39, 59) of the first mandrel (38, 56), and the channel area (70) of the first channel layer (34) part wise between the first side surface of the first dielectric mandrel (38, 56) and the section (43) of the gate electrode and partially between the second side surface of the first mandrel (38, 56) and the section (43) of the gate electrode, wherein the channel region (70) of the second channel layer (34) is partially positioned between the side surface of the second dielectric mandrel (38, 56) and the section (43) of the gate electrode, and wherein the first channel layer (34) and the second channel layer (34) are composed of a two-dimensional material.
  15. Procedure according to Claim 14 , wherein the first channel layer (34) and the second channel layer (34) are formed before the first dielectric mandrel (38, 56) and the second dielectric mandrel (38, 56) are formed.
  16. Procedure according to Claim 14 , wherein the first channel layer (34) and the second channel layer (34) are formed after the first dielectric mandrel (38, 56) and the second dielectric mandrel (38, 56) are formed.
  17. Procedure according to one of the Claims 14 until 16 , wherein the first channel layer (34) and the second channel layer (34) are formed before the gate electrode is formed.

Description

BACKGROUND The present invention relates to semiconductor device manufacturing and integrated circuits and in particular structures for a field-effect transistor and methods for forming a structure for a field-effect transistor. Complementary metal-oxide semiconductor (CMOS) processes can be used to build p-type and n-type field-effect transistors, which are used, for example, to construct logic cells. Field-effect transistors generally comprise a channel region within a semiconductor body, a source, a drain, and a gate electrode above the body. When a control voltage exceeding a characteristic threshold voltage is applied to the gate electrode, a carrier flux occurs in the channel region between the source and the drain to generate a device output current. Nanosheet field-effect transistors represent a type of non-planar field-effect transistor that can be fabricated with increased packing density in an integrated circuit. A nanosheet field-effect transistor comprises multiple nanosheet channel layers arranged in a structured stack of layers over the top surface of a substrate, and source/drain regions connected to the lateral ends of the nanosheet channel layers. The nanosheet channel layers are initially arranged in the structured stack with sacrificial layers containing a material (e.g., silicon-germanium) that alternates with the nanosheet channel layers and can be selectively etched with respect to the material (e.g., silicon) representing the nanosheet channel layers. The source/drain regions can be formed by epitaxial growth of semiconductor material from the lateral ends of the nanosheet channel layers. The sacrificial layers are etched and removed to expose the nanosheet channel layers and provide space for the formation of a gate electrode. Sections of the gate electrode can surround all sides of the individual nanosheet channel layers in a gate-all-around configuration. During operation with a control voltage applied to the gate electrode, the horizontal flux of carriers in the nanosheet channel layers generates the device output current. Nanosheet field-effect transistors can experience scaling difficulties because reductions in nanosheet thickness eventually reach a point where quantum confinement significantly degrades performance. Additionally, short-channel effects can limit the ability to continue shrinking the gate length. As such, limitations regarding electrostatic control can restrict the scaling of nanosheet field-effect transistors. From the US 2015 / 0 041 873 A1 A vertical ferroelectric field-effect transistor is known. This comprises an insulating core surrounded by a layer of a transition metal dichalcogenide material, which in turn is surrounded by a gate dielectric. The gate dielectric is surrounded by a conductive gate material. Furthermore, it is from the US 10 388 732 B1 A field-effect transistor structure is known in which a plurality of channel layers are stacked and connected to a source/drain region. A multi-section gate structure surrounds the plurality of channel layers, the plurality of channel layers comprising a two-dimensional semiconductor material. The source/drain regions also consist of a two-dimensional semiconductor material. Improved structures for a field-effect transistor and methods for forming a structure for a field-effect transistor are needed. BRIEF SUMMARY In embodiments of the invention, a structure for a field-effect transistor is provided. The structure comprises a first mandrel composed of a dielectric material, wherein the first mandrel comprises a plurality of side surfaces, the plurality of side surfaces comprising a first side surface and a second side surface; a second mandrel composed of the dielectric material, wherein the second mandrel comprises a side surface, and the second mandrel is arranged above the first mandrel; and a gate electrode having a section that is enveloped around the first side surface and the second side surface of the first mandrel. The structure further comprises a first channel layer comprising a channel region, wherein the channel region of the first channel layer extends around all of the side surfaces of the first mandrel and is partially positioned between the first side surface of the first mandrel and the gate electrode section, and partially between the second side surface of the first mandrel and the gate electrode section; and a second channel layer comprising a channel region that is partially positioned between the side surface of the second mandrel and the gate electrode section. The first channel layer and the second channel The layers are composed of a two-dimensional material. In embodiments of the invention, a method for forming a field-effect transistor is provided. The method comprises forming a first channel layer and a second channel layer, both channel layers comprising a channel region; forming a first dielectric mandrel comprising a plurality of side surfaces; forming a second dielectric mand