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DE-102022129065-B4 - Semiconductor device with a Germanium region arranged in a semiconductor substrate

DE102022129065B4DE 102022129065 B4DE102022129065 B4DE 102022129065B4DE-102022129065-B4

Abstract

SPAD device with: a silicon substrate (102) with a recess (104) in a top side (102u) of the silicon substrate (102); a p-region (106) which is located in the silicon substrate (102) under a bottom of the recess (104); an n-avalanche region (108) located in the silicon substrate (102) below the p-region (106) and meeting the p-region (106) at a pn junction (110); a germanium region (112) which is arranged in the recess (104) above the pn junction (110); and an intrinsically conductive silicon region (118) located between an upper part of the p-region (106) and a lower part of the germanium region (112), wherein the intrinsically conductive silicon region (118) is configured to act as an electron channel extending over the entire distance between the pn junction (110) and the germanium region (112), wherein the germanium region has the following: an upper germanium region with a first p-doping concentration; and a lower germanium region with a second p-doping concentration, wherein the second p-doping concentration is lower than the first p-doping concentration, and the SPAD device further features the following: a sidewall germanium region that extends continuously along an outer sidewall of the germanium region and traverses the upper germanium region and the lower germanium region.

Inventors

  • Hung-Chang Chien
  • Hsiang-Lin Chen
  • Jung-I Lin
  • Ming-Chieh Hsu
  • Kuan-Chieh Huang
  • Tzu-Jui WANG
  • Myles Huang
  • Chen-Jong Wang
  • Dun-Nian Yaung
  • Yi-Shin Chu

Assignees

  • TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Dates

Publication Date
20260513
Application Date
20221103
Priority Date
20220520

Claims (12)

  1. SPAD device comprising: a silicon substrate (102) with a recess (104) in a top surface (102u) of the silicon substrate (102); a p-region (106) located in the silicon substrate (102) below a bottom surface of the recess (104); an n-avalanche region (108) located in the silicon substrate (102) below the p-region (106) and intersecting the p-region (106) at a pn junction (110); a germanium region (112) located in the recess (104) above the pn junction (110); and an intrinsically conductive silicon region (118) located between an upper part of the p-region (106) and a lower part of the germanium region (112), wherein the intrinsically conductive silicon region (118) is configured to act as an electron channel extending over the entire distance between the pn junction (110) and the germanium region (112), wherein the germanium region comprises: an upper germanium region with a first p-doping concentration; and a lower germanium region with a second p-doping concentration, wherein the second p-doping concentration is lower than the first p-doping concentration, and wherein the SPAD device further comprises: a sidewall germanium region extending continuously along an outer sidewall of the germanium region and traversing the upper germanium region and the lower germanium region.
  2. SPAD device according to Claim 1 , which further comprises: a p-surface region (120) located in the silicon substrate (102) and laterally enclosing the intrinsically conductive silicon region (118) and extending upwards along inner side walls of the recess (104) in the silicon substrate (102) and along outer side walls of the germanium region (112).
  3. SPAD device according to Claim 1 or 2 , wherein the germanium region (112) meets the silicon substrate (102) at a Ge-Si interface (117) consisting of a Ge-Si alloy with a lattice constant of 0.566 nm to 0.543 nm, wherein the Ge-Si interface (117) is defined where outer sidewalls and a bottom surface of the germanium region (112) meet inner sidewalls and a recessed top surface (102u) of the silicon substrate (102), respectively.
  4. SPAD device according to any of the preceding claims, further comprising: a lateral n-connection region (114) extending laterally from outer edges of the n-avalanche region (108) across outer sidewalls of the germanium region (112); and a vertical n-connection region (116) extending upwards from outer edges of the lateral n-connection region (114) to a top surface (102u) of the silicon substrate (102).
  5. SPAD device according to Claim 4 , wherein the n-avalanche region (108), the lateral n-connection region (114) and the vertical n-connection region (116) collectively form an essentially U-shaped profile that substantially encloses the p-region (106) and the germanium region (112).
  6. SPAD device according to one of the preceding claims, further comprising a silicon cap (128a, 128b) arranged in the recess (104) above a top surface (102u) of the germanium area (112).
  7. SPAD device according to Claim 6 , wherein the top surface (102u) of the silicon cap (128a, 128b) is at the same level as a top surface of the silicon substrate (102).
  8. SPAD device according to Claim 6 or 7 , which further features: a sidewall germanium area (126) located in an outer edge of the recess (104) and having a top surface (102u) that meets a bottom surface of the silicon cap (128a, 128b).
  9. A method comprising: Obtaining a semiconductor substrate (600); Performing ion implantation to create a lateral interconnect region (114) beneath a top surface (102u) of the semiconductor substrate (600); Performing ion implantation to create a vertical interconnect region (116), wherein the vertical interconnect region (116) and the lateral interconnect region (114) contact each other to form a guard ring; Producing, in the top surface (102u) of the semiconductor substrate (600), a recess (104) which is laterally enclosed by the guard ring and defined by a recessed top surface (102u) of the semiconductor substrate (600) and inner side walls of the semiconductor substrate (600); Generating a germanium region (112) in the recess (104), and after generating the lateral interconnection region (116), growing an epitaxial silicon region over an upper region of the semiconductor substrate (600), wherein the vertical interconnection region (114) is generated in the epitaxial silicon region; and/or in which the germanium region (112) has outer sidewalls that extend laterally beyond outer edges of the pn junction (110).
  10. Procedure according to Claim 9 , wherein the lateral connection region (116) is an n semiconductor material, and the method further comprises: generating a p region (106) prior to the growth of the epitaxial silicon region, which contacts the n semiconductor material at a pn junction (110).
  11. Procedure according to Claim 9 or 10 , wherein the p-region (106) is generated under a bottom surface of the recess (104) at a distance from it, such that an intrinsically conductive silicon region separates a bottom surface of the germanium region (112) from a top surface of the p-region (106).
  12. Procedure according to one of the Claims 9 until 11 , which further comprises: fabricating a silicon cap (128a, 128b) over a top surface (102u) of the germanium region (112), wherein the silicon cap (128a, 128b) directly contacts a top surface (102u) of the germanium region (112) without an oxide separating the germanium region (112) from the silicon cap (128a, 128b), wherein the silicon cap (128a, 128b) is grown in situ in the same facility or chamber as the germanium region (112).

Description

background A single-photon avalanche diode (SPAD) is a solid-state photodetector in the same family as photodiodes and avalanche photodiodes (APDs). Like photodiodes and APDs, a SPAD is arranged around a pn junction of a semiconductor that can be irradiated with ionizing radiation, such as gamma, X-ray, beta, and/or alpha particles, along with a broad portion of the electromagnetic spectrum from ultraviolet (UV) wavelengths through visible wavelengths to infrared (IR) wavelengths. During operation, a carrier generated by photon absorption is accelerated by an electric field within the device to a kinetic energy sufficient to overcome the ionization energy of the solid material, knocking electrons out of atoms within the material. A large avalanche of current carriers grows exponentially and can be triggered by a single carrier initiated by just one photon. A SPAD is capable of detecting individual photons, providing short-term trigger pulses that can be counted. It can also be used to determine the arrival time of the incoming photon based on the high velocity that builds up in the avalanche. US 2021 / 0 375 959 A1 Disclosure shows a photovoltaic cell comprising a germanium-containing well embedded in a single-crystal silicon substrate and extending to a proximal horizontal surface of the single-crystal silicon substrate, wherein the germanium-containing well contains germanium in an atomic percentage of more than 50%. A silicon-containing cover structure is located on an upper surface of the germanium-containing well and contains silicon in an atomic percentage of more than 42%. The silicon-containing cover structure prevents oxidation of the germanium-containing well. A photovoltaic compound can be formed within or across the well by implanting dopants of a first conductivity type and dopants of a second conductivity type. US 2021 / 0 091 239 A1 discloses a photosensor device, wherein the photosensor device comprises a substrate with a silicon layer on a front side, a photosensitive element projecting into the silicon layer and at least partially surrounded by it, and a composite layer arranged between the photosensitive element and the silicon layer and surrounding the photosensitive element, wherein the composite layer comprises a first material and a second material different from the first material. WO 2021 / 215 066 A1 Disclosing an optical detector comprising: a pixel region in which pixels with a photoelectric conversion unit are arranged multiple times in a matrix, each photoelectric conversion unit comprising: a first semiconductor unit divided by partitions; a second semiconductor unit located closer to a first surface between the first surface and a second surface positioned on opposite sides of the first semiconductor unit, the second semiconductor unit containing germanium; a light absorption unit provided on the second semiconductor unit, the light absorption unit absorbing light incident on the second semiconductor unit and generating a charge carrier; and a multiplier unit provided on the first semiconductor unit, the multiplier unit performing an avalanche multiplication of the charge carrier generated by the light absorption unit. Further state of the art is known from DISMUKES, JP; EKSTROM, L.; PAFF, RJ: Lattice parameters and density in germanium-silicon alloys. In: The journal of physical chemistry, Vol. 68, 1964, No. 10, pp. 3021-3027. - ISSN 0022-3654 . The invention is defined in the claims. Brief description of the drawings Aspects of this disclosure are best understood with reference to the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with industry practice, various features are not shown to scale. Rather, the dimensions of the various features may have been arbitrarily enlarged or reduced for the sake of clarity. 1 shows a sectional view of some embodiments of an integrated chip with a SPAD device having a germanium area embedded in a silicon substrate. 2 shows a sectional view of some embodiments of an integrated chip with a SPAD device having a germanium area embedded in a silicon substrate. 3A shows a sectional view of some embodiments of an integrated chip with a SPAD device having a germanium area embedded in a silicon substrate. 3B shows a band gap diagram of some embodiments of a SPAD device, which 3A corresponds. The 4 and 5 shown are sectional views of some embodiments of an integrated chip with a SPAD device, each having a germanium area embedded in a silicon substrate. The 6 to 14 show a manufacturing process according to some embodiments. The 15 to 21 show a further manufacturing process according to other embodiments. The 22 to 29 show a further manufacturing process according to other embodiments. 30 shows a flowchart of a manufacturing process according to some embodiments. Detailed description The disclosure below provides many different embodiments or examples for implementing various featur