DE-102024132812-A1 - Method for creating a pseudo-model of an electrical circuit

Abstract

The invention relates to a method for creating a pseudomodel 1 of an electrical circuit for estimating test coverage based on a design model 2 of the electrical circuit. In this process, a first, second, and third data set 4, 6, 8 are successively generated using a first, second, and third trained neural network 3, 5, 7, respectively. The neural networks 3, 5, 7 extract and categorize first, second, and third model data from the design model 2 and the data sets 4, 6, 8 known from previous process steps. Finally, the data sets 4, 6, 8 and the design model 2 are combined to form a pseudomodel 1 that approximates the electrical circuit. The first, second, and third model data each comprise a different piece of information: a component category for each component of the electrical circuit, a pin category for each pin of each component of the electrical circuit, and a network category for each network formed from several electrically connected pins.

Inventors

• Norbert Münch
• Ricardo Wenzel
• Sven Leidenfrost
• Alexander Labrada Diaz

Assignees

• Göpel electronic GmbH

Dates

Publication Date

20260513

Application Date

20241111

Claims (10)

1. A method for creating a pseudomodel (1) of an electrical circuit for estimating test coverage based on a design model (2) of the electrical circuit, comprising the following steps: - Creating a first dataset (4) from the design model (2) by a first trained neural network (3), which extracts and categorizes initial model data, - Creating a second dataset (6) from the design model (2) and the first dataset (4) by a second trained neural network (5), which extracts and categorizes additional model data, - Creating a third dataset (8) from the design model (2), the first dataset (4), and the second dataset (6) by a third trained neural network (7), which extracts and categorizes additional model data, - Combining the first, second, and third datasets (4, 6, 8) and the design model (2) into a pseudomodel (1) that approximates the electrical circuit, wherein the first, second, and third model data each contain a different piece of information. include: i. a component category for each component of the electrical circuit, ii. a pin category for each pin of each component of the electrical circuit, and iii. a net category for each net formed from several electrically connected pins.
2. Procedure according to Claim 1 , where - the first model data includes the net category, - the second model data includes the component category and - the third model data includes the pin category.
3. Procedure according to Claim 1 or 2 , where each network is assigned one of the following minimum values characterizing its affiliation as the network category: Power supply, Earth, JTAG-TMS, JTAG-TCK, JTAG-TDIO.
4. Procedure according to one of the Claims 1 until 3 , where each component is assigned one of the following minimum values characterizing its affiliation as the component category: resistor, capacitor, inductor, transistor, diode, relay, connector, switch, test point, RAM, flash memory, boundary scan IC.
5. Procedure according to one of the Claims 1 until 4 , where each pin is assigned one of the following minimum values characterizing its affiliation as the pin category: power supply, ground, RAM address, RAM data, RAM control signal, FLASH address, FLASH data, FLASH control signal, JTAG-TMS, JTAG-TCK, JTAG-TDIO.
6. Procedure according to one of the Claims 1 until 5 , where when creating the first data set (4), when creating the second data set (6) or when creating the third data set (8) user input is prioritized by the trained neural networks (3, 5, 7).
7. Procedure according to one of the Claims 1 until 6 , wherein, prior to merging into a pseudo-model (1), the first, second or third neural network (3, 5, 7) repeats the creation of the respective data set (4, 6, 8) based on all available data sets (4, 6, 8).
8. Procedure according to one of the Claims 1 until 7 , wherein at least the following information from the design model (2) is processed by the trained neural networks (3, 5, 7): component identifier, component type, component package identifier, signal name, signal assignment, number of pins, number of networks, number of components, component pin count, information on the design of the networks.
9. Method for determining test coverage for an electrical circuit, wherein - first a pseudomodel (1) according to one of the Claims 1 until 8 is generated, - the pseudomodel (1) is passed to a test generator (9) which is suitable for creating a test pattern for an electrical circuit, - the test generator (9) creates a test pattern for the pseudomodel and - the test coverage of the electrical circuit is estimated on the basis of the test pattern (9) for the pseudomodel (1).
10. A computer program that is executable on a computer and causes the computer to execute a method according to the preceding claims.

Description

The invention relates to a method for creating a pseudo-model of an electrical circuit for estimating test coverage based on a design model of the electrical circuit. Testing complex electrical circuits is a crucial step in the development process of electronic devices. With the continuous advancements in semiconductor technology and the increasing functionality of circuits, whether in microprocessors, communication modules, or control units, the demands on the reliability and precision of these systems are also rising. This involves not only testing individual components, but also examining the entire system for functionality under various operating conditions. A key challenge in testing is finding the right balance between test depth and test effort. Due to the complexity of modern circuits, it is often impossible to fully replicate every possible combination of input signals and operating states. Therefore, efficient test strategies are needed that ensure the most comprehensive possible verification of relevant error sources without unnecessarily lengthening or increasing the cost of the test process. A key aspect of such testing procedures is determining test coverage, which describes how many possible errors or conditions are checked during the test relative to the total number of possible errors. High test coverage means that the probability of undetected errors in the system is low. A method for estimating test coverage is described in the US 2004 / 0 044 973 A1 This reveals potential defects. Potential defects are numerically recorded without considering how they would be tested. The defects are then evaluated using a point system that indicates whether the respective defect would be detected in a test. Subsequently, test coverage is determined based on the assigned points. The potential defects are estimated by categorizing and evaluating the components and connections of the underlying electrical circuit. For highly complex circuits, determining test coverage is often a complex and time-consuming process. Generating the data for test coverage analysis typically requires extensive manual input. One approach is to use a design model of the electrical circuit, which might be a CAD file containing all relevant information about the printed circuit board, as a basis. To determine test coverage, all components of the design model must be classified and modeled. This data is then passed to a test generator, which uses the circuit architecture and predefined test criteria to determine suitable test patterns to cover the broadest possible range of failure scenarios. A test generator requires information such as the component class, pin properties, and a functional description. Currently, this information is entered or assigned by the user, as test coverage cannot be determined without a corresponding component description. This results in a usable pseudo-model of the electrical circuit for the test generator, which can then be used to determine test coverage. However, this manual approach is very labor-intensive. The object of the invention is to reduce the effort required to determine test coverage using a test generator and to increase accuracy. This task is solved by a method for creating a pseudo-model of an electrical circuit for estimating test coverage based on a design model of the electrical circuit, which includes the following steps: - Creating an initial dataset from the design model using an initial trained neural network, which extracts and categorizes initial model data, - Creating a second dataset from the design model and the first dataset using a second trained neural network, which extracts and categorizes the second model data. - Creating a third dataset from the design model, the first dataset, and the second dataset using a third trained neural network, which extracts and categorizes the third model data, and - Combining the first, second, and third data sets and the construction model into a pseudo-model that approximates the electrical circuit, where the first, second, and third model data each comprise a different piece of the following information: i. a component category of each component of the electrical circuit, ii. a pin category of each pin of each component of the electrical circuit and iii. a net category of any net formed from several electrically connected pins. The result of this method is not a complete model of the electrical circuit, but rather a pseudo-model that approximates the circuit and primarily contains the data a test generator needs to determine test coverage. The pseudo-model need not even be a model of any specific circuit, as long as the test generator can use the data from the pseudo-model to determine test coverage for the underlying electrical circuit. To determine test coverage, it is not absolutely necessary to plan every possible test in full; rather, it is sufficient to determine the general applicability of a specific test and its coverage within