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DE-102024210760-A1 - Method for synchronizing the switch-on process of parallel-connected transistors

DE102024210760A1DE 102024210760 A1DE102024210760 A1DE 102024210760A1DE-102024210760-A1

Abstract

The invention relates to a method (100) for synchronizing a switch-on process of parallel-connected transistors (2), comprising: - Recording (101) a respective gate-source voltage profile during the turn-on process of the transistors (2), - Determining (102) individual delays of switching transients during the turn-on process for each transistor (2) based on changes in the slope of the respective gate-source voltage, - Initiating (103) a configuration of at least one gate driver (3) based on the determined individual delays to synchronize the turn-on process of the parallel-connected transistors (2), wherein the at least one gate driver (3) is used to drive the transistors (2). Furthermore, the invention relates to a power module, a computer program, a device and a storage medium for this purpose.

Inventors

  • Dominik Alexander Ruoff
  • Muhammad Muneeb Alam
  • Jochen Streit
  • Hadiuzzaman Syed

Assignees

  • Robert Bosch Gesellschaft mit beschränkter Haftung

Dates

Publication Date
20260513
Application Date
20241108

Claims (11)

  1. Method (100) for synchronizing a turn-on process of parallel-connected transistors (2), comprising: - Acquiring (101) a respective gate-source voltage profile during the turn-on process of the transistors (2), - Determining (102) individual delays of switching transients during the turn-on process for each transistor (2) based on changes in the slope of the respective gate-source voltage profile, - Initiating (103) a configuration of at least one gate driver (3) based on the determined individual delays to synchronize the turn-on process of the parallel-connected transistors (2), wherein the at least one gate driver (3) is used to drive the transistors (2).
  2. Procedure (100) according to Claim 1 , characterized in that the determination (102) comprises: - analyzing the recorded respective waveform of the gate-source voltage, - identifying a time point at which a drain-source voltage of the respective transistor (2) begins to commutate, wherein this time point is reflected in the form of a change in the slope of the gate-source voltage in the respective waveform, wherein the individual delays correspond to a time interval from a switch-on until the respective identified time points.
  3. Procedure (100) according to Claim 1 or 2 , characterized in that one of the transistors (2) is used as a reference transistor and, during configuration, the specific individual delay of the at least one further transistor (2) is adjusted to the specific individual delay of the reference transistor (2).
  4. Method (100) according to one of the preceding claims, characterized in that the transistors (2) are used in a half-bridge configuration with a full DC link voltage and without load current during the detection (101).
  5. Method (100) according to one of the preceding claims, characterized in that the method (100) further comprises: - using the at least one gate driver (3) with the applied specific individual delays in a regular operating mode to drive the transistors (2).
  6. Procedure (100) according to Claim 5 , characterized in that , during the detection (101), a higher resistance value is used for a turn-on resistor (4) of the transistors (2) than in the regular operating mode after configuring the at least one gate driver (3), wherein the turn-on resistor (4) is arranged in a respective turn-on path of the transistors (2).
  7. Power module (1), comprising: - at least two transistors (2) connected in parallel, - at least one gate driver (3) for controlling a respective transistor (2) or at least two transistors (2), - a respective on-resistor (4) arranged in a respective on-path of the transistors (2), - a slope detector circuit (5) for detecting a respective gate-source voltage profile of the respective transistors (2), - a data processing device (10) for carrying out the method (100) according to one of the preceding claims.
  8. Performance module (1) according to Claim 7 , characterized in that the at least two parallel-connected transistors (2) are arranged in a half-bridge configuration and at least one transistor (2) is a high-side transistor and the at least one further transistor (2) is a low-side transistor.
  9. Computer program (20), comprising instructions which, when the computer program (20) is executed by a computer (10), cause the computer to perform the procedure (100) according to one of the Claims 1 until 6 to execute.
  10. Device (10) for data processing, which is configured to perform the method (100) according to one of the Claims 1 until 6 to execute.
  11. Computer-readable storage medium (15), comprising instructions which, when executed by a computer (10), cause it to perform the steps of the procedure (100) according to one of the Claims 1 until 6 to execute.

Description

The invention relates to a method for synchronizing the switch-on process of parallel-connected transistors. Furthermore, the invention relates to a power module, a computer program, a device, and a storage medium for this purpose. State of the art Parallel connection of transistors such as silicon carbide metal oxide semiconductor field-effect transistors (SiC MOSFETs) in a power module to increase output power is a well-established technique. However, due to tolerances in the MOSFET manufacturing process, parameter variations can occur in the transistors during switching transitions. These variations—threshold voltage, transconductance, Miller charge, and input capacitance—lead to asymmetrical switching between the parallel-connected transistors. Few solutions for correcting this switching asymmetry have been described in the prior art, and most of them employ either an additional high-speed circuit in the power path to detect the parameters or an ASIC current source gate driver to detect and correct the asymmetry. Disclosure of the invention The invention relates to a method with the features of claim 1, a power module with the features of claim 7, a computer program with the features of claim 9, a device with the features of claim 10, and a computer-readable storage medium with the features of claim 11. Further features and details of the invention will become apparent from the respective dependent claims, the description, and the drawings. Features and details described in connection with the method according to the invention naturally also apply in connection with the power module, the computer program, the device, and the computer-readable storage medium according to the invention, and vice versa, so that a reciprocal reference is always possible with regard to the disclosure of the invention. The invention relates in particular to a method for synchronizing a switch-on process of parallel-connected transistors such as metal oxide semiconductor field-effect transistors (MOSFETs), IGBTs (bipolar transistors with insulated gate electrodes) or GaN transistors, comprising: - Recording the respective curve, in particular a change in the slope of the respective curve, of a gate-source voltage (V<sub>GS</sub> ) during the turn-on process of the transistors, - Determining individual delays of switching transients during the turn-on process for each transistor based on changes in the slope of the respective gate-source voltage curve, - Initiating a configuration of at least one gate driver based on the specified individual delays to synchronize the turn-on process of the parallel-connected transistors, so that, in particular advantageously, current commutation in the parallel-connected transistors begins simultaneously, wherein the at least one gate driver is used to control the transistors. A MOSFET switches on, in particular, when a sufficiently high voltage (V<sub>GS</sub> ) is applied between the gate and the source. This voltage ensures, in particular, that the MOSFET transitions to the conducting state and current flows through the drain-source channel. The gate driver preferably provides this voltage and can build it up and then reduce it again to precisely control the switching process. The method according to the invention makes it possible to ensure that the parallel-connected transistors reach their threshold voltage simultaneously and thus become current-carrying synchronously. This leads, in particular, to a reduced switching asymmetry in the current flow during the turn-on process, which in turn can enable an improvement in overall performance, a reduction in losses, and/or lower electromagnetic emissions. Furthermore, a reduced blanking time and thus higher short-circuit robustness can be provided. Furthermore, it is conceivable that determining includes: - Analyzing the recorded respective course of the gate-source voltage, for example by means of a slope detector circuit, wherein preferably a slope of the respective course is analyzed, - Identifying a point in time at which a drain-source voltage of the respective transistor begins to commutate, whereby this point in time is reflected in the form of a change in the slope of the gate-source voltage in the respective curve, The individual delays correspond to the time span from power-on to the respective identified points in time. In other words, this allows, in particular, a precise determination of the delay of each transistor by analyzing the gate-source voltage and identifying the point in time at which the drain-source voltage changes. The determined individual delays can then enable fine-tuning of the driver parameters, which can lead to improved synchronization of the current commutation of all transistors. Optionally, one of the transistors can be used as a reference, and during configuration, the specific individual delay of at least one other transistor is adjusted to match the specific individual delay of the reference transistor, fo