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DE-102024210861-A1 - Circuit arrangement for controlling a half-bridge circuit

DE102024210861A1DE 102024210861 A1DE102024210861 A1DE 102024210861A1DE-102024210861-A1

Abstract

The invention relates to a circuit arrangement (5) with a monitoring device (20) for monitoring a control device (1) for a half-bridge circuit (3), wherein the control device (1) is configured to generate control signals for high-side and low-side gate drivers (HSGD, LSGD) for controlling high-side and low-side FET switches (HST, LST) of the half-bridge circuit (3), and wherein the monitoring device (20) is configured to generate a turn-off/enable control signal (DISset) for controlling a turn-off/enable of the gate drivers (HSGD, LSGD). According to the invention, the integrated circuit (10) further comprises a signal processing device (30) configured to generate high-side and low-side shutdown/enable signals (HSdis, LSdis) for the high-side and low-side gate drivers (HSGD, LSGD) based on the shutdown/enable control signal (DISset), such that when the shutdown/enable control signal (DISset) changes to the shutdown of the gate drivers (HSGD, LSGD), the high-side shutdown/enable signal (HSdis) changes immediately and the low-side shutdown/enable signal (LSdis) changes after a delay (Δtdis), whereas when the shutdown/enable control signal (DISset) changes to the enable of the gate drivers (HSGD, LSGD), the low-side shutdown/enable signal (LSdis) changes immediately and the high-side shutdown/enable signal (HSdis) changes after a time delay (Δtdis). Delay (Δten) changes.

Inventors

  • Andreas Wunderlich

Assignees

  • Schaeffler Technologies AG & Co. KG

Dates

Publication Date
20260513
Application Date
20241112

Claims (9)

  1. Circuit arrangement (5) comprising a monitoring device (20) for monitoring the functionality of a control device (1) provided for controlling a half-bridge circuit (3), in which the control device (1) is configured to generate a high-side control signal (HSpwm) for controlling a high-side gate driver (HSGD) for controlling at least one high-side FET switch (HST) of the half-bridge circuit (3) and a low-side control signal (LSpwm) for controlling a low-side gate driver (LSGD) for controlling at least one low-side FET switch (LST) of the half-bridge circuit (3), and in which the monitoring device (20) is configured to generate, depending on a result of the monitoring, a digital turn-off/enable control signal (DISset) for controlling a turn-off/enable of the two gate drivers (HSGD, LSGD), wherein the circuit arrangement (5) further comprises a signal processing device (30) comprises a device configured to generate, based on the turn-off/enable control signal (DISset), a digital high-side turn-off/enable signal (HSdis) for the high-side gate driver (HSGD) and a digital low-side turn-off/enable signal (LSdis) for the low-side gate driver (LSGD), such that when the turn-off/enable control signal (DISset) changes to turn off the gate drivers (HSGD, LSGD), the high-side turn-off/enable signal (HSdis) changes immediately and the low-side turn-off/enable signal (LSdis) changes only after a time delay (Δtdis), whereas when the turn-off/enable control signal (DISset) changes to enable the gate drivers (HSGD, LSGD), the low-side turn-off/enable signal (LSdis) changes immediately and the high-side turn-off/enable signal (HSdis) changes only after a time delay (Δtdis). a time delay (Δten) changes.
  2. Circuit arrangement (5) according to Claim 1 , wherein the circuit arrangement (5) is designed as an integrated circuit (10).
  3. Circuit arrangement (5) according to Claim 2 , wherein the integrated circuit (10) is designed as an ASIC or microcontroller component.
  4. Circuit arrangement (5) according to Claim 2 or 3 , wherein the signal processing device (30) comprises an edge detection device (31, 32) for detecting rising edges and/or falling edges of the shutdown/enabling control signal (DISset).
  5. Circuit arrangement (5) according to Claim 4 , wherein the edge detection device (31, 32) has a first edge detector (31) for detecting rising edges and a second edge detector (32) for detecting falling edges of the shutdown/enabling control signal (DISset).
  6. Circuit arrangement (5) according to Claim 4 or 5 , wherein the signal processing device (30) of the edge detection device (31, 32) has a signal delay device (33, 34) downstream.
  7. Circuit arrangement (5) according to one of the preceding Claims 2 until 6 , further comprising a self-test device (40) for monitoring the functionality of the signal processing device (30), wherein the self-test device (40) is configured to evaluate the shutdown/enabling control signal (DISset) supplied to the signal processing device (30) and the high-side and low-side shutdown/enabling signals (HSdis, LSdis) generated by the signal processing device (30).
  8. Use of a circuit arrangement (5) according to one of the preceding Claims 2 until 7 for monitoring the functionality of a control device (1) designed as a microcontroller for controlling a half-bridge circuit (3).
  9. Use according Claim 8 on board a vehicle.

Description

The present invention relates to a circuit arrangement for controlling a half-bridge circuit and to the use of such a circuit arrangement. In the field of power electronics, for example in power converters (e.g. DC/DC converters or DC/AC converters), controllable half-bridge circuits with one or more half-bridges are often used, each consisting of a series connection of two controllable semiconductor switches (high-side FET switch and low-side FET switch) supplied with a supply voltage, in order to provide a respective output voltage at an output node between the two semiconductor switches. Such a half-bridge can be operated, for example, using PWM control (or another modulation method) to switch the two FET switches on and off in a complementary manner. When the half-bridge is supplied with a DC voltage applied to the series connection of the FET switches, an AC voltage is provided at the output node according to the control method (e.g., PWM control). With several half-bridges operated in parallel, the individual phase voltages and resulting phase currents required for a multi-phase (e.g., three-phase) AC machine can thus be generated, for example, in an inverter. The complementary switching on and off of the two FET switches of a half-bridge, high-side FET switch and low-side FET switch, caused by the control signal, means that switching on one FET switch (e.g., high-side FET switch) is accompanied by switching off the other FET switch (e.g., low-side FET switch), and vice versa. In order to achieve the steepest possible edges of the output voltages during switching operations in the half-bridge circuit and thus reduce electrical losses, the high-side and low-side control signals are nowadays usually generated by a microcontroller, especially in the automotive sector, and output to the high-side and low-side gate drivers, which generate sufficiently powerful gate control signals that are applied to the gates (control terminals) of the FET switches. However, if the operating range of the microcontroller or the control unit containing the microcontroller is exceeded, e.g. due to over- or undervoltage in the electrical supply of this unit, error-free control of the half-bridge circuit is no longer guaranteed and therefore, in such a fault case, an asynchronous intervention is carried out by the specially provided monitoring device, e.g., a so-called safety computer or "monitoring unit". The monitoring device monitors the functionality of the control unit intended for controlling the half-bridge circuit and is designed to generate a digital shutdown/enable control signal for controlling the shutdown/enablement of the gate drivers, depending on the result of this monitoring and, if applicable, other input variables, e.g., from a power supply or other monitoring devices. Thus, if, for example, a fault event is detected by the monitoring device during operation of the half-bridge circuit, safety can be maintained by outputting a shutdown/enable control signal to shut down the gate drivers. Upon detection of an error event, the gate drivers can be advantageously switched off by means of a corresponding shutdown/enable control signal (for shutdown), in order to switch off all the high-side FET switches and the low-side FET switches, for example. It is an object of the present invention to provide a circuit arrangement that enables reliable shutdown/release of high-side and low-side gate drivers, particularly in power electronics applications. The problem is solved by the features of the independent patent claims. Advantageous embodiments are characterized in the dependent claims. According to a first aspect, the problem is solved by a circuit arrangement comprising a monitoring device for monitoring the functionality of a control device intended for controlling a half-bridge circuit, wherein the control device is configured to generate a high-side control signal for controlling a high-side gate driver for controlling at least one high-side FET switch of the half-bridge circuit and a low-side control signal for controlling a low-side gate driver for controlling at least one low-side FET switch of the half-bridge circuit. The monitoring device is configured to generate, depending on a result of the monitoring, a digital shutdown/enable control signal for controlling a shutdown. The circuit arrangement further comprises a signal processing device configured to generate a digital high-side turn-off/enable signal for the high-side gate driver and a digital low-side turn-off/enable signal for the low-side gate driver based on the turn-off/enable control signal, such that when the turn-off/enable control signal changes to turn off the gate drivers, the high-side turn-off/enable signal changes immediately and the low-side turn-off/enable signal changes only after a time delay, whereas when the turn-off/enable control signal changes to enable the gate drivers, the low-side turn-off/enable signal changes immediately and th