DE-102025003892-A1 - Semiconductor component with input buffer circuit

Abstract

An exemplary apparatus comprises: a first input circuit coupled between a common source line and a first circuit node, wherein the first input circuit is configured to be controlled by a first signal; a second input circuit coupled between the common source line and a second circuit node, wherein the second input circuit is configured to be controlled by a second signal; an amplifier circuit configured to amplify a potential difference between the first and second circuit nodes; and an auxiliary current path configured to allow current to flow from the common source line to the first and second circuit nodes independently of the first and second signals.

Inventors

• Shun NISHIMURA

Assignees

• MICRON TECHNOLOGY, INC.

Dates

Publication Date

20260513

Application Date

20251106

Priority Date

20241111

Claims (20)

1. Device comprising: a differential amplifier circuit with a pair of a first and a second input transistor; a first auxiliary transistor connected in parallel to the first input transistor; and a second auxiliary transistor connected in parallel to the second input transistor, the first and second auxiliary transistors being configured to always be in an ON state.
2. Device according to Claim 1 , where the first and second auxiliary transistors are each smaller than the first and second input transistors.
3. Device according to Claim 1 , wherein a control electrode of the first auxiliary transistor is short-circuited with a control electrode of the second auxiliary transistor.
4. Device according to Claim 1 , wherein the first input transistor is configured to be controlled by externally supplied input data, and wherein the second input transistor is configured to be controlled by a reference potential with respect to the input data.
5. Device according to Claim 4 , further comprising a common-source transistor connected between a first supply line and a common source of the first and second input transistors, wherein the common-source transistor has a control electrode supplied with an internal data strobe signal.
6. Device according to Claim 1 , where each of the first and second auxiliary transistors has the same conductivity type as each of the first and second input transistors.
7. A device comprising: a first input circuit coupled between a common source line and a first circuit node, wherein the first input circuit is configured to be controlled by a first signal; a second input circuit coupled between the common source line and a second circuit node, wherein the second input circuit is configured to be controlled by a second signal; an amplifier circuit configured to amplify a potential difference between the first and second circuit nodes; and an auxiliary current path configured to allow current to flow functionally from the common source line to the first and second circuit nodes, independently of the first and second signals.
8. Device according to Claim 7 , wherein the auxiliary current path includes a first transistor connected in parallel to the first input circuit and a second transistor connected in parallel to the second input circuit.
9. Device according to Claim 8 , wherein the first input circuit includes a third transistor connected between the common source line and the first circuit node, wherein the second input circuit includes a fourth transistor connected between the common source line and the second circuit node, and wherein each of the first and second transistors is smaller than each of the third and fourth transistors.
10. Device according to Claim 8 , wherein a control electrode of the first transistor is short-circuited with a control electrode of the second transistor.
11. Device according to Claim 10 , where the control electrode of the first and second transistors is set to an active level.
12. Device according to Claim 10 , furthermore comprising a control circuit configured to control a level of the control electrodes of the first and second transistors.
13. Device according to Claim 10 , wherein the control electrode of each of the first and second transistors is supplied with an active level in a first operating mode, and wherein the control electrode of each of the first and second transistors is supplied with an inactive level in a second operating mode.
14. Device according to Claim 10 , wherein the auxiliary current path further comprises a fifth transistor connected in parallel to the first input circuit and a sixth transistor which is connected in parallel to the second input circuit.
15. Device according to Claim 14 , further comprising a control circuit configured to control a level of the control electrodes of the first and second transistors and to control a level of the control electrodes of the fifth and sixth transistors.
16. Device according to Claim 7 , wherein the amplifier circuit comprises: a first transistor with a control electrode coupled to the first circuit node; a second transistor with a control electrode coupled to the second circuit node; and a flip-flop circuit configured to operate based on the current flowing through the first and second transistors.
17. Device according to Claim 16 , further comprising a third transistor connected between a supply line and the common source line, wherein the third transistor has a control electrode supplied with an internal data strobe signal.
18. Device according to Claim 17 , where the first signal contains externally supplied input data.
19. Device according to Claim 18 , where the second signal is a reference potential with respect to the input data.
20. Device comprising: a first and a second supply line, each supplied with a first and a second supply potential that are different from each other; a first transistor connected between the first supply line and a common source line; a second transistor connected between the common source line and a first circuit node; a third transistor connected between the common source line and a second circuit node; a fourth transistor connected between the first circuit node and the second supply line; a fifth transistor connected between the second circuit node and the second supply line; an amplifier circuit configured to amplify a potential difference between the first and second circuit nodes; a sixth transistor connected in parallel with the first transistor; and a seventh transistor connected in parallel to the second transistor, whereby each of the first, second, third, sixth and seventh transistors has a first conductivity type, whereby each of the fourth and fifth transistors has a second conductivity type different from the first conductivity type, whereby each of the first, second, third, fourth and fifth transistors has a control electrode supplied with an internal data strobe signal, and whereby each of the sixth and seventh transistors has a control electrode short-circuited to the second supply line.

Description

BACKGROUND There is a case where a differential input buffer, which compares the level of an input signal and the level of a reference potential, is used for a semiconductor device, such as a DRAM. With such a differential input buffer, the characteristics of one transistor forming a circuit on the input side and the characteristics of another transistor forming a circuit on the reference side must be matched. BRIEF DESCRIPTION OF THE DRAWINGS 1 is a block diagram showing a configuration of a semiconductor storage device according to an embodiment of the present invention;2 is a block diagram showing a configuration of the main components of a data control circuit; and3A-3C These are circuit diagrams of a data latch circuit. DETAILED DESCRIPTION Various embodiments of the present invention are explained in detail below with reference to the accompanying drawings. The following detailed description refers to the accompanying drawings, which illustrate certain aspects and various embodiments of the present invention. The detailed description contains sufficient detail to enable those skilled in the art to implement these embodiments of the present invention. Other embodiments may also be used, and structural, logical, and electrical modifications may be made without departing from the scope of the present invention. The various embodiments disclosed herein are not necessarily mutually exclusive, since some of the disclosed embodiments may be combined with one or more other disclosed embodiments to form new embodiments. 1 is a block diagram showing a configuration of a semiconductor memory device 10 according to an embodiment of the present invention. The in 1 The semiconductor memory device 10 shown is an LPDDR5 DRAM and comprises a memory cell array 11. When the memory cell array 11 is accessed, an instruction address signal CA is input from an external source into an instruction address port 12. The instruction address signal CA is fed to an access control circuit 13. The access control circuit 13 is synchronized with complementary clock signals CKT and CKC, respectively, which are input into clock ports 14 and 15, respectively. This circuit decodes the instruction address signal CA, counts latencies, and performs other functions. When an instruction contained in the command address signal CA specifies a read operation, the access control circuit 13 performs a read access to a memory cell contained in the memory cell array 11 based on an address contained in the command address signal CA. The read data DQ from the accessed memory cell is output externally via a data I/O port 17 and a data control circuit 16. When the instruction contained in the command address signal CA specifies a write operation, the write data DQ input to the data I/O port 17 is transferred to the memory cell array 11 via an input buffer circuit 20 contained in the data control circuit 16. The write data DQ is input to the memory cell array 11 while being synchronized with complementary data strobe signals DQST and DQSC, which are supplied to the data strobe ports 18 and 19, respectively. The write data DQ transferred to memory cell array 11 is written to the memory cell contained in memory cell array 11, based on the address contained in the instruction address signal CA. 2 is a block diagram showing a configuration of the main components of the data control circuit 16. As in 2 As shown, the data control circuit 16 comprises a gating circuit 22 that receives data strobe signals DQST and DQSC via an input buffer 21. The internal data strobe signals DS and DSF output by the gating circuit 22 correspond to the data strobe signals DQST and DQSC, respectively. The internal data strobe signals DS and DSF are fed into a divider circuit 23. By dividing the internal data strobe signals DS and DSF, the divider circuit 23 generates four-phase internal data strobe signals DQS0, DQS90, DQS180, and DQS270. If the phase of the internal data strobe signal DQS0 is 0°, then the phases of the internal data strobe signals DQS90, DQS180, and DQS270 are 90°, 180°, and 270°, respectively. The internal data strobe signals DQS0, DQS90, DQS180, and DQS270 are fed to input buffer 20. The input buffer 20 includes a data latch circuit 200, which is connected to the internal data- Strobe signal DQS0 is synchronized to hold the write data DQ. A data latch circuit 201 is synchronized with the internal data strobe signal DQS90 to hold the write data DQ. A data latch circuit 202 is synchronized with the internal data strobe signal DQS180 to hold the write data DQ. A data latch circuit 203 is synchronized with the internal data strobe signal DQS270 to hold the write data DQ. The write data IDQ0, IDQ90, IDQ180, and IDQ270, respectively, which are held or stored in data latch circuits 200 to 203, are transferred to the memory cell array 11. Data latch circuits 200, 201, 202, and 203 each comprise a DFE (Decision Feedback Equalizer) circuit 200A, a DFE circuit 201A, a DFE