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DE-102025106805-A1 - Semiconductor devices and methods for their manufacture

DE102025106805A1DE 102025106805 A1DE102025106805 A1DE 102025106805A1DE-102025106805-A1

Abstract

Semiconductor devices and fabrication processes are provided in which a lower metal is produced over a substrate and treated to create a first oxygen-free zone. A first dielectric material is deposited over the lower metal and structured to expose the lower metal. A capacitor is then fabricated within the first dielectric material.

Inventors

  • Man-Yun WU
  • Hsiao-Kuan Wei
  • HSUAN-MING HUANG

Assignees

  • TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Dates

Publication Date
20260513
Application Date
20250224
Priority Date
20250221

Claims (20)

  1. A method for fabricating a semiconductor device, comprising: fabrication of a lower metal over a substrate; treating the lower metal to remove oxygen and create a first oxygen-free zone; depositing a first dielectric material over the lower metal; structuring the first dielectric material to expose the lower metal; and fabrication of a capacitor in the first dielectric material.
  2. Procedure according to Claim 1 , wherein when treating the lower metal a part of a second dielectric material is also treated, the second dielectric material being arranged below the lower metal.
  3. Procedure according to Claim 2 , which further includes oxidizing a top side of the second dielectric material prior to producing the bottom metal.
  4. Procedure according to Claim 2 or 3 , wherein the second dielectric material contains silicon nitride.
  5. Method according to any of the preceding claims, wherein the production of the lower metal comprises the production of titanium niride.
  6. A method according to any of the preceding claims, further comprising oxidizing a portion of the lower metal after structuring the first dielectric material.
  7. Method according to one of the preceding claims, wherein structuring the first dielectric material creates multiple openings that expose the lower metal.
  8. A method for fabricating a semiconductor device, comprising: depositing a first dielectric layer over a substrate; oxidizing a top surface of the first dielectric layer to create a first oxidized region; depositing a bottom metal over the top surface of the first dielectric layer; oxidizing a top surface of the bottom metal to create a second oxidized region; structuring the bottom metal to expose a portion of the first oxidized region; treating the entire second oxidized region and a portion of the first oxidized region to remove oxygen; depositing a second dielectric layer over the bottom metal; and fabrication a capacitor through the second dielectric layer and in electrical contact with the bottom metal.
  9. Procedure according to Claim 8 , which further includes re-oxidation of the top surface of the lower metal after deposition of the second dielectric layer.
  10. Procedure according to Claim 8 or 9 , whereby the treatment is carried out at least partially by exposing the second oxidized area to a plasma.
  11. Procedure according to Claim 10 , where the plasma is a nitrogen plasma.
  12. Procedure according to one of the Claims 8 until 11 , wherein the lower metal contains titanium niride.
  13. Procedure according to one of the Claims 8 until 12 , wherein the first dielectric layer contains silicon nitride.
  14. Procedure according to one of the Claims 8 until 13 , wherein the manufacture of the capacitor includes the manufacture of a metal-insulator-metal capacitor.
  15. Semiconductor device comprising: a first dielectric layer over a substrate, wherein the first dielectric layer has a first top surface, the first top surface comprising a first oxidized part and a first oxygen-free part; a bottom metal over the first oxidized part, the bottom metal having a second top surface, the second top surface comprising a second oxidized part and a second oxygen-free part; and a capacitor arranged over the second oxidized part.
  16. Semiconductor device according to Claim 15 , wherein the lower metal contains titanium niride.
  17. Semiconductor device according to Claim 15 or 16 , wherein the first dielectric layer contains silicon oxide.
  18. Semiconductor device according to one of the Claims 15 until 17 , wherein the capacitor makes physical contact with the second oxidized part at several points.
  19. Semiconductor device according to one of the Claims 15 until 18 , where the capacitor is a metal-insulator-metal capacitor.
  20. Semiconductor device according to one of the Claims 15 until 19 , which further comprises a second dielectric layer surrounding the capacitor, the second dielectric layer containing silicon nitride.

Description

Priority claim and cross-reference The present application claims priority over the preliminary US patent application filed on November 12, 2024, under file number 63/719.212 , which is incorporated into the present application by reference. background Semiconductor devices are used in various electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by successively depositing insulating or dielectric material layers, conductive material layers, and semiconductor material layers onto a semiconductor substrate. The different material layers are then structured using lithography and etching processes to create circuit components and elements on the substrate. The semiconductor industry is constantly improving the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continuously reducing the smallest feature size, thus enabling the integration of more components in a given area. However, reducing the smallest feature size introduces further problems in each of the processes used, which need to be addressed. Brief description of the drawings Aspects of this disclosure are best understood with reference to the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with industry practice, various features are not shown to scale. Rather, the dimensions of the various features may have been arbitrarily enlarged or reduced for the sake of clarity. 1 shows a fabrication of a lower metal over a substrate, according to some embodiments. 2 shows a placement of a first photoresist, according to some embodiments. 3 shows a structuring of the lower metal, according to some embodiments. 4 shows a first treatment process according to some embodiments. 5 shows a deposition of a dielectric layer over the lower metal, according to some embodiments. 6 shows a planarization of the dielectric layer above the lower metal, according to some embodiments. 7 shows a placement of a second photoresist, according to some embodiments. 8 shows a structuring of the dielectric layer, according to some embodiments. The 9A and 9B show a production of further conductive vias and redistribution layers, according to some embodiments. Detailed description The disclosure below provides many different embodiments or examples for implementing various features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the fabrication of a first element above or on top of a second element in the description below may include embodiments in which the first and second elements are fabricated in direct contact, and it may also include embodiments in which additional elements can be fabricated between the first and second elements, such that the first and second elements are not in direct contact. Furthermore, reference numerals and/or letters may be repeated in the various examples in the present disclosure. This repetition serves for simplicity and clarity and does not, in itself, prescribe a relationship between the various embodiments and/or configurations discussed. Furthermore, spatially relative terms, such as "located below,""under,""lower,""locatedabove,""upper," and the like, can be used here to simply describe the relationship of one element or structural element to one or more other elements or structural elements shown in the figures. In addition to the orientation shown in the figures, the spatially relative terms should encompass other orientations of the device in use or operation. The device can be oriented differently (rotated by 90° or in a different orientation), and the spatially relative The descriptors used here can be interpreted accordingly. The following describes embodiments based on a specific embodiment in which a treatment is performed on a lower metal to minimize over-etching during the fabrication of a three-dimensional metal-insulator-metal capacitor. However, the embodiments presented here are intended only to illustrate the ideas outlined and are not meant to limit the embodiments to the specific structures discussed herein. The ideas presented can be implemented in many different structures and processes, and all such embodiments are intended to be entirely within the scope of protection of the embodiments. Now let's move on to... 1 Here is shown an initial structure for the fabrication of a 3DMIM (three-dimensional metal-insulator-metal device) comprising a substrate 101, a first dielectric layer 103, conductive structural elements 105, a first etch stop layer 107, a second dielectric layer 109, and a bottom metal 111. The substrate 101 can be essentially conductive or semiconducting and may consist of solid silicon, doped or undoped, or an active