DE-102025107207-A1 - Silicide areas and the methods for forming them

Abstract

A process comprises forming a source/drain region, forming a contact etch stop layer over the source/drain region, forming an interlayer dielectric over the contact etch stop layer, forming a first contact plug in the interlayer dielectric and the contact etch stop layer, and performing an etching process to form a trench in the interlayer dielectric and the contact etch stop layer. The source/drain region and the first contact plug are exposed to the trench. The process further comprises performing a silicide formation process to form a silicide region on a surface of the source/drain region and etching a metal layer deposited on dielectric regions and in the trench. The dielectric regions are exposed at the time the silicide formation process is initiated. A second contact plug is formed in the trench.

Inventors

• Hsin Wang
• Kai-Chieh Yang
• Shih-Jung Ho
• Ku-Feng Yang
• Wei-Yen Woon
• Szuya Liao

Assignees

• TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Dates

Publication Date

20260513

Application Date

20250226

Priority Date

20250205

Claims (20)

1. A method comprising: Forming a source/drain region; Forming a contact etch stop layer over the source/drain region; Forming an interlayer dielectric over the contact etch stop layer; Forming a first contact plug in the interlayer dielectric and the contact etch stop layer; Performing an etching process to form a trench in the interlayer dielectric and the contact etch stop layer, exposing the source/drain region and the first contact plug to the trench; Performing a silicide formation process to form a silicide region on a surface of the source/drain region; Etching a metal layer deposited on dielectric regions and in the trench, the dielectric regions being exposed at the time the silicide formation process is initiated; and Forming a second contact plug in the trench.
2. Procedure according to Claim 1 , wherein the metal layer is etched in a plasma-free and hydrogen-free (H2 - free) environment.
3. Procedure according to Claim 2 , wherein both the silicide formation process and the etching of the metal layer are carried out using titanium chloride (TiCl 4 ) as a process gas and hydrogen (H 2 ) is used during the silicide formation process.
4. Procedure according to one of the Claims 1 until 3 , further comprising: after the silicide formation process, performing a nitrogen treatment process to form a metal silicon nitride layer over the silicide area, thereby forming a metal nitride layer on the first contact plug; and performing a wet etching process to remove the metal nitride layer.
5. Procedure according to Claim 4 , which further includes carrying out a vacuum fracturing process to form a metal oxide layer over the metal nitride layer, with the metal oxide layer also being removed by the wet etching process.
6. Procedure according to Claim 5 , wherein the wet etching process is carried out using a chemical solution containing ozonated DI water and hot DI water.
7. Procedure according to one of the Claims 1 until 6 , further comprising: selectively forming a passivation layer over the silicide region; and removing a metal compound layer from the first contact plug, wherein the metal compound layer is selected from the group consisting of a metal nitride layer, a metal oxide layer and combinations thereof, and wherein, when the metal compound layer is removed, the passivation layer is located over the silicide region.
8. Procedure according to Claim 7 , wherein the passivation layer is formed by soaking a wafer having the silicide region in a chemical solution, whereby a chemical in the chemical solution adheres above the silicide region to form the passivation layer.
9. Procedure according to Claim 8 , where the chemical solution has a pH value in a range between about 2 and about 6.
10. Procedure according to one of the Claims 7 until 9 , further comprising, after the metal compound layer has been removed, removal of the passivation layer, whereby the second contact plug is formed after the passivation layer has been removed.
11. A method comprising: forming a lower source/drain region; forming a first contact etch stop layer over the lower source/drain region; forming a first interlayer dielectric over the first contact etch stop layer; forming an upper source/drain region over the first interlayer dielectric, wherein the upper source/drain region overlaps the lower source/drain region; forming a second contact etch stop layer over the upper source/drain region; forming a second interlayer dielectric over the second contact etch stop layer; forming a first contact plug having a top surface higher than the upper source/drain region and a bottom surface lower than the lower source/drain region; performing an etching process to form a contact opening in the second interlayer dielectric and the second contact etch stop layer, wherein the first contact plug is exposed to the contact opening; forming a dielectric lining in the contact opening; Forming a silicide region above and in contact with the upper source/drain region, with a metal layer simultaneously forming on the dielectric surface clothing is formed; performing a first etching process to remove the metal layer; performing a nitrogen treatment process, forming a metal silicon nitride layer over the silicide area and a metal nitride layer over the first contact plug; performing a second etching process to etch the metal nitride layer and expose the first contact plug; and forming a second contact plug in the contact opening.
12. Procedure according to Claim 11 , where the second etching process involves a wet etching process.
13. Procedure according to Claim 12 , which further includes the formation of a passivation layer prior to the second etching process to protect the metal silicon nitride layer when the metal nitride layer is etched.
14. Procedure according to Claim 13 , wherein the passivation layer is selectively formed by saturating the metal silicon nitride layer in a chemical solution, causing a chemical in the chemical solution to adhere to the metal silicon nitride layer.
15. Procedure according to Claim 14 , wherein the passivation layer is selectively formed using a zeta potential difference between the metal silicon nitride layer and the metal nitride layer.
16. Procedure according to Claim 14 or 15 , wherein the chemical solution contains chemicals selected from the group consisting of phosphoric acid, silane adhesion promoters, polyacrylic acid and combinations thereof.
17. A method comprising: Forming a silicon-containing region; Forming a silicide region over the silicon-containing region; Forming a metal silicon nitride layer over the silicide region; and Forming a metal structural element over the metal silicon nitride layer, wherein, after the metal structural element has been formed, an element selected from the group consisting of phosphorus, carbon, sulfur, fluorine, and combinations thereof, is present in the metal structural element, the metal silicon nitride layer, and the silicide region.
18. Procedure according to Claim 17 , wherein the element has a peak concentration at an interface between the metal silicon nitride layer and the metal structural element.
19. Procedure according to Claim 17 or 18 , further comprising: before the metal structure element is formed, forming a passivation layer over the metal silicon nitride layer; performing an etching process to remove a metal nitride layer on an additional metal structure element located adjacent to the silicide area, wherein during the etching process the passivation layer protects the metal silicon nitride layer; and removing the passivation layer, wherein the metal structure element is formed after the passivation layer has been removed.
20. Procedure according to one of the Claims 17 until 19 , wherein the silicon-containing region is located in a source/drain region of a transistor and wherein the silicide region is a source/drain silicide region of the transistor.

Description

PRIORITY CLAIM AND CROSS-REFERENCE This application claims priority of the provisional US patent application no. 63/718,021 , filed on November 8, 2024 and entitled “Clean Method at MD-VLI Interface”, which is incorporated by reference into the present application. BACKGROUND Semiconductor devices are used in a variety of electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic equipment. Semiconductor devices are typically manufactured by successively depositing insulating or dielectric layers, conductive layers, and semiconductor layers onto a semiconductor substrate, and structuring the various material layers using lithography to create circuit components and elements. The semiconductor industry is continuously improving the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continuously reducing the minimum feature size, which makes it possible to integrate more components into a given area. However, reducing the minimum feature size introduces additional problems that need to be addressed. BRIEF DESCRIPTION OF THE DRAWINGS Aspects of this disclosure are best understood with reference to the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with industry practice, various features are not shown to scale. In fact, the dimensions of the various features may have been arbitrarily enlarged or reduced for the sake of clarity. 1A and 1B until 14 are views of intermediate stages in the formation of CFETs and silicide regions in accordance with some embodiments. 15 to 19 are views of intermediate stages in the formation of CFETs and silicide regions in accordance with some embodiments. 20 and 21 Illustrate zeta potentials of TiO2 and WO3 in accordance with some embodiments. 22 illustrates a distribution profile of an element in a passivation layer in accordance with some embodiments. 23 illustrates a flowchart for forming CFETs and silicide regions in accordance with some embodiments. DETAILED DESCRIPTION The following disclosure provides many different embodiments, or examples, for implementing various features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first structural element over or on top of a second structural element in the following description may include embodiments in which the first and second structural elements are formed in direct contact, and may also include embodiments in which additional structural elements may be formed between the first and second structural elements, such that the first and second structural elements might not be in direct contact. In addition, the present disclosure may repeat reference numbers and/or letters in the various examples. This repetition serves the purpose of simplification and clarity and does not itself establish a relationship between the different embodiments and/or configurations discussed. Furthermore, spatially relative terms such as "underlying," "below," "under," "overlying," "above," and the like may be used herein to facilitate description and to describe the relationship of one element or structural element to another element(s) or structural element(s), as illustrated in the figures. These spatially relative terms are intended to encompass various orientations of the component in use or operation in addition to the orientation depicted in the figures. The device may be oriented differently (rotated by 90 degrees or in other orientations), and the spatially relative descriptive terms used herein may be interpreted accordingly. Complementary field-effect transistors (CFETs), silicide regions, contact connectors, and the method for forming them are provided. In accordance with some embodiments of the present disclosure, the silicide regions are A silicide region is formed by the deposition of metal, and simultaneously, the metal reacts with the epitaxial semiconductor to form a silicide region. A dry etching process can be performed to remove the metal that is undesirably deposited on the surfaces of dielectric regions. A nitrogen treatment process is carried out to form a metal silicon nitride layer on the silicide region, which in turn causes a metal nitride layer to form on any exposed metallic area. A subsequent wet etching process can be used to remove the metal nitride layer. It is welcome that, while the CFET encompasses gate-all-around transistors (GAA transistors) (such as nanostructured FETs) being discussed, the principle of the present disclosure can also be applied to the formation of contact connectors that link other transistor types, such as planar transistors, fin field-effect transistors (FinFETs), and the like. Throughout the description, the terms "FET" and "transistor" a