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DE-102025110885-B3 - INTEGRATED CIRCUIT WITH GALVANIC INSULATION STRUCTURE AND GATE DRIVER CIRCUIT

DE102025110885B3DE 102025110885 B3DE102025110885 B3DE 102025110885B3DE-102025110885-B3

Abstract

An integrated circuit (500) comprises a semiconductor layer (130) with a first section (131) in a first device area (310) and a second section (132) in a second device area (320). A galvanic isolation structure (330) is formed between the first section (131) and the second section (132) of the semiconductor layer (130). A capacitive coupling element (200) is formed on a first surface (139) of the semiconductor layer (130). The capacitive coupling element (200) comprises a first lower electrode (210) in the first device area (310) and a capacitor dielectric (250) that separates the first lower electrode (210) from an upper electrode (290) extending over the galvanic isolation structure (330). The first lower electrode (210) is signal-connected to a first circuit element (315) in the first device area (310). The upper electrode (290) is functionally connected to a second circuit element (325) in the second device area (320).

Inventors

  • Dirk Manger
  • Lars Müller-Meskamp
  • Ralf Rudolf
  • Henning Feick

Assignees

  • INFINEON TECHNOLOGIES AUSTRIA AG

Dates

Publication Date
20260513
Application Date
20250320
Priority Date
20241220

Claims (17)

  1. Integrated circuit comprising: a semiconductor layer (130) comprising a first section (131) in a first device area (310) and a second section (132) in a second device area (320); a galvanic isolation structure (330) formed between the first section (131) and the second section (132) of the semiconductor layer (130); and a capacitive coupling element (200) formed on a first surface (139) of the semiconductor layer (130), wherein the capacitive coupling element (200) comprises a first lower electrode (210) in the first device area (310) and a capacitor dielectric (250) separating the first lower electrode (210) from an upper electrode (290) extending over the galvanic isolation structure (330), wherein the first lower electrode (210) is signal-connected to a first circuit element (315) formed in the first device area (310) and the upper electrode (290) is functionally connected to a second circuit element (325) formed in the second device area (320).
  2. Integrated circuit according to Claim 1 , wherein the upper electrode (290) and the second circuit element (325), which is formed in the second device area (320), are directly electrically connected.
  3. Integrated circuit according to Claim 1 , wherein the capacitive coupling element (200) further comprises a the second lower electrode (220) in the second device area (320) comprises the capacitor dielectric (250) further separating the second lower electrode (220) from the upper electrode (290) and the second lower electrode (220) being signal-connected to the second circuit element (325) formed in the second device area (320).
  4. Integrated circuit according to one of the preceding claims, wherein the galvanic isolation structure (330) extends from a first surface (139) of the semiconductor layer (130) into the semiconductor layer (130) and isolates the first section (131) and the second section (132) of the semiconductor layer (130) from each other up to a breakdown voltage of at least 200 V.
  5. Integrated circuit according to one of the preceding claims, wherein the upper electrode (290) comprises a section of an uppermost metal layer (180) of the integrated circuit (500).
  6. Integrated circuit according to one of the preceding claims, further comprising: a polyimide layer (190) covering the upper electrode (290).
  7. Integrated circuit according to one of the preceding claims, wherein the upper electrode (290) comprises a first electrode section (291) in the first device area (310), a second electrode section (292) in the second device area (320) and a narrow connecting section (293) connecting the first electrode section (291) and the second electrode section (292).
  8. Integrated circuit according to Claim 7 , wherein the connecting section (293) has a length along a direction that directly connects the first electrode section (291) and the second electrode section (292) in a horizontal plane parallel to the first surface (139) of the semiconductor layer (130), and a width (w3) in the horizontal plane orthogonal to the length extent, wherein the width extent (w3) is smaller than horizontal extents of the first electrode section (291) and the second electrode section (292) parallel to the width extent (w3) of the connecting section (293).
  9. Integrated circuit according to one of the Claims 7 or 8 , wherein the first electrode section (291) of the upper electrode (290) extends laterally beyond the first lower electrode (210) and/or the second electrode section (292) of the upper electrode (290) extends laterally beyond the second lower electrode (220).
  10. Integrated circuit according to one of the Claims 7 until 9 , wherein a horizontal shape of the first electrode section (291) parallel to the first surface (139) and/or the second electrode section (292) of the upper electrode (290) are rounded with a radius of at least 5 µm.
  11. Integrated circuit according to any one of the preceding claims, further comprising: a first trench insulation structure (261) extending from the first surface (139) into the semiconductor layer (130) and laterally surrounding a first embedded region (133) of the semiconductor layer (130) directly below the first lower electrode (210), and/or a second trench insulation structure (262) extending from the first surface (139) into the semiconductor layer (130) and laterally surrounding a second embedded region (134) of the semiconductor layer (130) directly below the second lower electrode (220).
  12. Integrated circuit according to one of the preceding claims, further comprising: a first protective conductor (281) formed along an edge of the first lower electrode (210), and/or a second protective conductor (282) formed along an edge of the second lower electrode (220).
  13. Integrated circuit according to Claim 12 , wherein the first protective conductor (281) is electrically connected to the first section (131) of the semiconductor layer (130) at a lateral distance from the first lower electrode (210) and/or the second protective conductor (282) is electrically connected to the second section (132) of the semiconductor layer (130) at a lateral distance from the second lower electrode (220).
  14. Integrated circuit according to Claim 13 , wherein the first conductive protective conductor (281) and the first lower electrode (210) are formed from different sections of a lower electrode metal layer, and/or wherein the second conductive protective conductor (282) and the second lower electrode (220) are formed from different sections of a lower electrode metal layer.
  15. Integrated circuit according to Claim 14 , further comprising: a first feed line (316) connecting the first circuit element (315) and the first lower electrode (210), wherein the first protective conductor (281) and a through section (317) of the first feed line (316) crossing the first protective conductor (281) are formed in different metal layers; and/or a second feed line (326) connecting the second circuit element (325) and the second lower electrode (220), wherein the second protective line (282) and a through section (327) of the second feed line (326) crossing the second protective line (282) are formed in different metal layers.
  16. Integrated circuit according to one of the preceding claims, further comprising: an insulating layer (120) formed on one side of the semiconductor layer (130) opposite the first surface (131).
  17. Gate driver circuit comprising: a semiconductor layer (130) comprising a first section (131) in a first device area (310) and a second section (132) in a second device area (320); a galvanic isolation structure (330) formed between the first section (131) and the second section (132) of the semiconductor layer (130); and a capacitive coupling element (200) formed on a first surface (139) of the semiconductor layer (130), wherein the capacitive coupling element (200) comprises a first lower electrode (210) in the first device area (310), a second lower electrode (220) in the second device area (320), and a capacitor dielectric (250) separating the first lower electrode (210) and the second lower electrode (220) from an upper electrode (290), wherein the first lower electrode (210) is signal-connected to a first circuit element (315) formed in the first device area (310), and the second lower electrode (220) is signal-connected to a second circuit element (325) formed in the second device area (320).

Description

TECHNICAL AREA The present disclosure relates to integrated high-voltage circuits with separate device areas and to gate driver circuits. BACKGROUND Integrated high-voltage circuits in CMOS (complementary metal-oxide-semiconductor) technology typically comprise a low-voltage region for interconnection with low-voltage CMOS control and/or sensor circuits and a high-voltage region for controlling high-voltage switches or analyzing high-voltage signals. Up to application voltages of several hundred volts, lightly doped semiconducting voltage junctions can separate the high-voltage region from the low-voltage region, and internal high-voltage semiconductor elements can transfer electrical signals between the two. At higher application voltages, such semiconducting voltage junctions require a considerably large chip area, and it becomes increasingly difficult to prevent unwanted voltage breakdown between the high-voltage and low-voltage regions. From the US 2020 / 058 688 A1 A CMOS image sensor is known. From the DE 10 2010 011 258 A1 A semiconductor device is disclosed comprising an N-type impurity region provided in a substrate, wherein a P-type RESURF layer is provided on a top side of the substrate in the N-type impurity region. The DE 10 2008 012 858 A1 Figure 1 shows semiconductor devices with at least two semiconductor regions. In one embodiment, the semiconductor regions of the semiconductor device are electrically isolated from each other by an insulator, and a deposited, structured metal layer extends over the semiconductor regions and over the insulator. The DE 10 2021 103 424 A1 discloses a microelectronic device comprising a first electrode, a second electrode arranged vertically below the first electrode and separated by a dielectric material, and a connecting wire electrically connected to the second electrode, wherein the first electrode comprises a notch arranged vertically above the connecting wire. There is a constant need to provide integrated high-voltage circuits with high-voltage breakdown capability and reliable internal data transmission. SUMMARY An integrated circuit comprises a semiconductor layer with a first section in a first device area and a second section in a second device area. A galvanic isolation structure is formed between the first and second sections of the semiconductor layer. A capacitive coupling element is formed on a first surface of the semiconductor layer. The capacitive coupling element comprises a first lower electrode in the first device area and a capacitor dielectric that separates the first lower electrode from an upper electrode extending across the galvanic isolation structure. The first lower electrode is signal-connected to a first circuit element in the first device area. The upper electrode is functionally connected to a second circuit element in the second device area. The galvanic isolation structure provides an area-efficient isolation structure for high nominal breakdown voltages. The capacitive coupling element ensures reliable signal transmission across the galvanic isolation with predictable transmission parameters, without compromising the galvanic isolation. BRIEF DESCRIPTION OF THE DRAWINGS The present disclosure is illustrated by way of example and without limitation in the figures of the accompanying drawings, in which the same reference numerals refer to similar or identical elements. The elements of the drawings are not necessarily to scale relative to one another. The features of the various illustrated examples may be combined, provided they are not mutually exclusive. 1A-1B Illustrating a schematic vertical cross-sectional view and a corresponding horizontal cross-sectional view of a section of an integrated circuit with a galvanic isolation structure and a capacitive coupling element for signal transmission over the galvanic isolation structure according to an embodiment relating to a capacitive coupling element having an upper electrode and a lower electrode. 2A-2B Figure 1 illustrates a schematic vertical cross-sectional view and a corresponding horizontal cross-sectional view of a section of an integrated circuit with a galvanic isolation structure and a capacitive coupling element for signal transmission over the galvanic isolation structure according to an embodiment relating to a capacitive coupling element having an upper electrode and two lower electrodes on both sides of the galvanic isolation structure. 3 Figure 1 illustrates a schematic top view of an integrated circuit with a galvanic isolation structure between a first device area and a second device area and with capacitive coupling elements for signal transmission between the first device area and the second device area according to one embodiment. 4 Figure 1 illustrates a schematic vertical cross-sectional view of a section of an integrated circuit with an upper electrode of a capacitive coupling element formed in a top metal layer, according to one embodiment. 5 Figure