DE-102025112123-A1 - Semiconductor Device Package and Manufacturing Process

DE102025112123A1DE 102025112123 A1DE102025112123 A1DE 102025112123A1DE-102025112123-A1

Abstract

In one embodiment, a method comprises: forming a package structure, wherein forming the package structure comprises: attaching multiple dies to a support substrate, performing an encapsulation process to surround the multiple dies with an encapsulation material, and forming a redistribution structure over the multiple dies and the encapsulation material, wherein the redistribution structure is electrically connected to the multiple dies, wherein the redistribution structure has a rectangular shape in a top view, wherein the rectangular shape has first parallel edges having a first width, and second parallel edges having a second width, wherein at least one of the first width and the second width is greater than 212 mm.

Inventors

Po-Ching Wu
Shih-Wei Chen
Meng-Tsan Lee
An-Jhih Su

Assignees

TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Dates

Publication Date: 20260513
Application Date: 20250328
Priority Date: 20250218

Claims (20)

A method comprising: Forming a package structure, wherein forming the package structure comprises: Attaching multiple dies to a support substrate; Performing an encapsulation process to surround the multiple dies with an encapsulation material; and Forming a redistribution structure over the multiple dies and the encapsulation material, wherein the redistribution structure is electrically connected to the multiple dies, the redistribution structure having a rectangular shape in a plan view, the rectangular shape having first parallel edges having a first width, and second parallel edges having a second width, wherein at least one of the first width and the second width is greater than 212 mm.
Procedure according to Claim 1 , wherein carrying out the encapsulation process includes applying a granulated potting compound to and around the multiple dies and over the support substrate.
Procedure according to Claim 2 , wherein the formation of the redistribution structure includes performing a slot coating process to form a dielectric layer of the redistribution structure over the encapsulation material and the multiple dies.
Procedure according to one of the Claims 1 until 3 , where forming the package structure further includes: forming screw holes that extend through the redistribution structure and the encapsulation material.
Procedure according to Claim 4 , wherein forming the package structure further comprises: coupling a voltage regulation module (VRM) and a connector to the redistribution structure; and forming an underfill in a gap between the VRM and the redistribution structure and in a gap between the connector and the redistribution structure.
Procedure according to Claim 5 , furthermore comprising: positioning the package structure in a space between a cooling plate and an input/output frame (I/O frame); and securing the package structure to the cooling plate and the I/O frame using screws extending through the screw holes in the redistribution structure and the encapsulation material.
Procedure according to one of the Claims 1 until 6 , where the first width is up to 510 mm and the second width is up to 515 mm.
A method for forming a system, wherein the method comprises: Forming a package structure, wherein forming the package structure comprises: Forming a first section of the package structure, wherein forming the first section of the package structure comprises: Forming a backside redistribution structure over a support substrate; Attaching a first plurality of dies to the backside redistribution structure; Performing a first encapsulation process to surround the first plurality of dies with a first encapsulation material; Forming a frontside redistribution structure over the first plurality of dies and the first encapsulation material; Attaching a second plurality of dies to the frontside redistribution structure; and performing a second encapsulation process to surround the second plurality of dies with a second encapsulation material, wherein the first section of the package structure has a rectangular shape in a plan view, the rectangular shape having first parallel edges having a first width and second parallel edges having a second width, wherein at least one of the first width and the second width is greater than 212 mm.
Procedure according to Claim 8 , wherein the first encapsulation process comprises the application of a granulated potting compound onto and around the first plurality of dies and via the rear redistribution structure.
Procedure according to Claim 8 or 9 , where forming the first section of the package structure further includes: forming conductive vias across, and in electrical connection with, the rear redistribution structure.
Procedure according to one of the Claims 8 until 10 , where the first plural of Dies includes at least one bridge die.
Procedure according to Claim 11 , where the first plurality of dies includes at least one integrated voltage regulator die (IVR die).
Procedure according to one of the Claims 8 until 12 , where forming the package structure further includes: coupling a first package component with a voltage regulation point of the first section of the package structure, wherein the first package component comprises a first substrate and a voltage regulation module (VRM) coupled to the first substrate.
Procedure according to Claim 13 , wherein forming the package structure further includes: coupling a second package component to a connection point of the first section of the package structure, wherein the second package component comprises a second substrate and a connector coupled to the second substrate.
System comprising: a package structure comprising: multiple dies coupled to a first side of a redistribution structure; and an encapsulation material on the first side of the redistribution structure, the encapsulation material surrounding each of the multiple dies, the package structure having a rectangular shape in a plan view, the rectangular shape having first parallel edges having a first width, and second parallel edges having a second width, and wherein at least one of the first width and the second width is greater than 212 mm.
System according Claim 15 , the package structure further includes: a voltage regulation module (VRM) and a connector that is coupled to a second side of the redistribution structure.
System according Claim 15 or 16 , wherein the encapsulation material comprises a granulated potting compound.
system according to one of the Claims 15 until 17 , further comprising: a thermal module located below and in contact with the package structure; and an input/output frame (I/O frame) located above the package structure, the package structure being situated in a space between the thermal module and the I/O frame.
System according Claim 18 , further comprising: screws extending through screw holes in the thermal module, the EA frame and the redistribution structure; and fasteners screwed onto the ends of the screws, the screws and fasteners securing the package structure between the thermal module and the EA frame.
System according Claim 19 , where the heating module is a cooling plate.

Description

PRIORITY CLAIM AND CROSS-REFERENCE This application claims priority over the preliminary application filed on 12 November 2024. US application no. 63/719,174 entitled “System on Panel”, which is hereby incorporated into the present text by reference. BACKGROUND The semiconductor industry has experienced rapid growth due to continuous improvements in the integration density of a wide variety of electronic components (e.g., transistors, diodes, resistors, capacitors, etc.). These improvements in integration density largely result from repeated reductions in the smallest possible feature size, allowing more components to be integrated into a given area. As a consequence of the increased demand in recent years for miniaturization, higher speed and bandwidth, as well as lower power consumption and latency, the need for smaller and more innovative encapsulation techniques for semiconductor dies has grown. As semiconductor technologies have advanced, stacked and bonded semiconductor devices have proven to be an effective alternative for further reducing the physical size of a semiconductor device. In a stacked semiconductor device, active circuits such as logic, memory, and processor circuits are at least partially fabricated on separate substrates and then physically and electrically connected to form a functional device. Such processes require sophisticated techniques, and improvements are desirable. BRIEF DESCRIPTION OF THE DRAWINGS Aspects of this disclosure are best understood with reference to the following detailed description, when read in conjunction with the accompanying figures. It should be noted that, in accordance with common industry practice, various structural elements are not drawn to scale. Rather, the dimensions of the various structural elements may be enlarged or reduced as necessary for the sake of clarity in this discussion. 1 Illustrates a cross-sectional view of an IC die according to some embodiments. 2 to 9 Illustrate cross-sectional views of intermediate steps during a process for forming a package structure according to some embodiments. 10A and 10B Illustrate top views of package structures according to some embodiments. 11 to 13 Illustrate cross-sectional views of intermediate steps during a process for assembling a system according to some embodiments. 14 to 19 Illustrate cross-sectional views of intermediate steps during a process for forming a package structure according to some embodiments. 20A and 20B Illustrate top views of package structures according to some embodiments. 21 illustrates a cross-sectional view of intermediate steps during a process for assembling a system according to some embodiments. DETAILED DESCRIPTION The following disclosure provides many different embodiments or examples for implementing various features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, only examples and are not intended to be limiting. For example, the formation of a first structural element over or on top of a second structural element in the following description may include embodiments in which the first and second structural elements are in direct contact, and may also include embodiments in which additional structural elements may be formed between the first and second structural elements, so that the first and second structural elements are not necessarily in direct contact. Furthermore, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition serves the purpose of simplicity and clarity and does not automatically establish a relationship between the various embodiments and/or arrangements discussed. Furthermore, spatially relative terms, such as "below", "under", "lower", "above", "upper", and the like, can be used in the present text to simplify the description and to express the relationship of one element or feature to one or more other elements or features, as shown in the figures. The spatially relative terms are intended to illustrate and describe the device. They are also meant to encompass other orientations of the device in use or operation besides the orientation shown in the figures. The device may also be oriented differently (rotated by 90 degrees, or in other orientations), and the spatially relative descriptors used in this text can be interpreted accordingly. Various embodiments include methods applied to the formation of a device package (for example, a system-on-panel device (SOP device)) comprising a redistribution structure having one or more semiconductor chips bonded to the redistribution structure and one or more package components bonded to a side of the redistribution structure opposite the one or more semiconductor chips. The one or more semiconductor chips may be surrounded by an encapsulation material, and the combination of the encapsulation material and the redistribution structure may be referred to as a