DE-102025112328-A1 - Memory circuits with common self-tracking reference circuit and method for operating the same

Abstract

A memory circuit comprises a first memory cell and a second memory cell coupled to a first sampling amplifier by a first bit line and a second bit line, respectively; a third memory cell and a fourth memory cell coupled to a second sampling amplifier by a third bit line and a fourth bit line, respectively; and a reference circuit configured to provide multiple reference current levels corresponding to different operating modes of the respective first through fourth memory cells. The reference circuit is alternately coupled to the first and third bit lines or to the second and fourth bit lines.

Inventors

• Zheng-Jun Lin
• Chung-Cheng Chou
• Yu-Der Chih
• Masayoshi Nakayama
• Atsuo Mangyo

Assignees

• TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Dates

Publication Date

20260513

Application Date

20250331

Priority Date

20250317

Claims (20)

1. A memory circuit comprising: a first memory cell and a second memory cell coupled to a first sampling amplifier by a first bit line and a second bit line, respectively; a third memory cell and a fourth memory cell coupled to a second sampling amplifier by a third bit line and a fourth bit line, respectively; and a reference circuit configured to provide multiple reference current levels corresponding to different operating modes of the respective first to fourth memory cells; wherein the reference circuit is alternately coupled to the first bit line and the third bit line or to the second bit line and the fourth bit line.
2. Memory circuit according to Claim 1 , where each of the first to fourth memory cells has a resistive direct access memory cell (RRAM cell).
3. Memory circuit according to Claim 1 or 2 , wherein the reference circuit comprises a first resistive element, a second resistive element, a third resistive element and a transistor array connected in series.
4. Memory circuit according to Claim 3 , where the transistor array comprises one transistor, four transistors, eight transistors, or sixteen transistors.
5. Memory circuit according to Claim 1 , further comprising: a first switch selectively coupled between the first bit line and the third bit line; a second switch selectively coupled between the first bit line and a first transistor switch connected to the reference circuit; a third switch selectively coupled between the third bit line and the first transistor switch connected to the reference circuit; a fourth switch selectively coupled between the second bit line and the fourth bit line; a fifth switch selectively coupled between the second bit line and a second transistor switch connected to the reference circuit; and a sixth switch coupled between the fourth bit line and the second transistor switch connected to the reference circuit.
6. Memory circuit according to Claim 5 , wherein the first to third switches are configured to be enabled, while the fourth to sixth switches are configured to be disabled, causing the first sampling amplifier to compare one of the multiple reference current levels with a first cell current flowing through the second memory cell, or causing the second sampling amplifier to compare one of the multiple reference current levels with a second cell current flowing through the fourth memory cell.
7. Memory circuit according to Claim 5 , wherein the first to third switches are configured to be disabled, while the fourth to sixth switches are configured to be enabled, causing the first sampling amplifier to compare one of the multiple reference current levels with a first cell current flowing through the first memory cell, or causing the second sampling amplifier to compare one of the multiple reference current levels with a second cell current flowing through the third memory cell.
8. Memory circuit according to Claim 1 , further comprising: a first switch selectively coupled between the first bit line and the third bit line; a first transistor switch selectively coupled between the first bit line and a reference line; a second transistor switch selectively coupled between the third bit line and the reference line; a second switch selectively coupled between the second bit line and the fourth bit line; a third transistor switch selectively coupled between the second bit line and the reference line; and a fourth transistor switch coupled between the fourth bit line and the reference line.
9. Memory circuit according to Claim 8 , wherein the reference line is coupled between the reference circuit and a source/drain terminal of each of the first to fourth transistor switches.
10. Memory circuit after one of the Claims 1 until 9 , where the operating modes include a normal read, a first write verification and a second write verification of each of the first to fourth memory cells.
11. A memory circuit comprising: a first memory cell and a second memory cell coupled to a first sampling amplifier by a first bit line and a second bit line, respectively; a third memory cell and a fourth memory cell coupled to a second sampling amplifier by a third bit line and a fourth bit line, respectively, wherein the first to fourth memory cells are each configured to exhibit a first resistance state or a second resistance state; and a reference circuit configured to provide multiple reference current levels for both the first and second sampling amplifiers.
12. Memory circuit according to Claim 11 , wherein a first of the several reference current levels corresponds to reading one of the first to fourth memory cells, a second of the several reference current levels corresponds to verifying whether the first resistance state is written to one of the first to fourth memory cells, and a third of the several reference current levels corresponds to verifying whether the second resistance state is written to one of the first to fourth memory cells.
13. Memory circuit according to Claim 11 or 12 , wherein the reference circuit comprises a first resistive element, a second resistive element, a third resistive element and a transistor array connected in series.
14. Memory circuit according to Claim 13 , where the transistor array comprises one transistor, four transistors, eight transistors, or sixteen transistors.
15. Memory circuit according to Claim 11 , further comprising: a first switch selectively coupled between the first bit line and the third bit line; a second switch selectively coupled between the first bit line and a first transistor switch connected to the reference circuit; a third switch selectively coupled between the third bit line and the first transistor switch connected to the reference circuit; a fourth switch selectively coupled between the second bit line and the fourth bit line; a fifth switch selectively coupled between the second bit line and a second transistor switch connected to the reference circuit; and a sixth switch coupled between the fourth bit line and the second transistor switch connected to the reference circuit.
16. Memory circuit according to Claim 15 , where the first to third switches are activated while the fourth to sixth switches are deactivated, or the first to third switches are deactivated while the fourth to sixth switches are activated.
17. Memory circuit according to Claim 11 , further comprising: a first switch selectively coupled between the first bit line and the third bit line; a first transistor switch selectively coupled between the first bit line and a reference line; a second transistor switch selectively coupled between the third bit line and the reference line; a second switch selectively coupled between the second bit line and the fourth bit line; a third transistor switch selectively coupled between the second bit line and the reference line; and a fourth transistor switch coupled between the fourth bit line and the reference line.
18. Memory circuit according to Claim 17 , wherein the first switch, the first transistor switch and the second transistor switch are activated, while the second switch, the third transistor switch and the fourth transistor switch are deactivated, or the first switch, the first transistor switch and the The second transistor switch is deactivated, while the second switch, the third transistor switch and the fourth transistor switch are activated.
19. Methods for operating memory circuits comprising: Activating a first group of switches to couple a first bit line and a second bit line to a reference circuit, while a second group of switches is deactivated to decouple a third bit line and a fourth bit line from the reference circuit, the reference circuit being configured to provide multiple reference current levels; Comparing a first cell current flowing through a first of several memory cells with a first of the multiple reference current levels, the first memory cell being coupled to a first sampling amplifier via the third bit line or the fourth bit line; Deactivating the first group of switches to decouple the first bit line and the second bit line from the reference circuit, while the second group of switches is activated to couple the third bit line and the fourth bit line to the reference circuit; and comparing a second cell current flowing through a second of the multiple memory cells with a second of the multiple reference current levels, wherein the second memory cell is coupled to a second sampling amplifier via the first bit line or the second bit line.
20. Procedure according to Claim 19 , where the multiple reference current levels correspond to different operating modes, each corresponding to one of the multiple memory cells.

Description

CROSS-REFERENCE TO RELATED REGISTRATION This application claims priority of the provisional US patent application no. 63/719,859 , submitted on November 13, 2024, which is incorporated into the present application by reference. BACKGROUND The semiconductor industry has experienced rapid growth due to continuous improvements in the integration density of a range of electronic components (e.g., transistors, diodes, resistors, capacitors, etc.). This improvement in integration density has largely resulted from repeated reductions in the minimum size of structural elements, allowing more components to be integrated into a given area. BRIEF DESCRIPTION OF THE DRAWINGS Aspects of this disclosure are best understood with reference to the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with industry practice, various features are not shown to scale. In fact, the dimensions of the various features may have been arbitrarily enlarged or reduced for the sake of clarity. 1 illustrates a block diagram of a memory circuit according to some embodiments. 2 illustrates a circuit diagram of a memory cell of the memory circuit of 1 according to some embodiments. 3 illustrates a schematic diagram of a section of the memory circuit of 1 according to some embodiments. 4 illustrates a circuit diagram based on the one in 3 The schematic diagram shown is configured according to some embodiments. 5 another circuit diagram, based on the one in 3 The schematic diagram shown is configured according to some embodiments. 6 illustrates waveforms of signals when the memory circuit is activated. 1 is operated according to some embodiments. 7 , 8 , 9 and 10 Each diagram illustrates an exemplary circuit diagram of a self-tracking reference circuit of the memory circuit of 1 according to some embodiments. 11 illustrates an exemplary circuit diagram of a self-tracking reference circuit of the memory circuit of 1 according to some embodiments. 12 illustrates a representation of an exemplary relationship between a cell current and a bit number according to some embodiments. 13 This is an exemplary flowchart of a procedure for operating the memory circuit of 1 according to some embodiments. 14 illustrates another schematic diagram of a section of the memory circuit of 1 according to some embodiments. 15 illustrates a circuit diagram based on the one in 14 The schematic diagram shown is configured according to some embodiments. 16 illustrates an exemplary circuit diagram of a global self-tracking reference circuit of the memory circuit of 14-15 according to some embodiments. 17 illustrates an exemplary circuit diagram of a local self-tracking reference circuit of the memory circuit of 14-15 according to some embodiments. 18 illustrates a block diagram of another memory circuit according to some embodiments. 19 , 20 and 21 Exemplary cross-sectional views of dummy columns illustrate how to form a self-tracking reference circuit of the memory circuit of 1 according to some embodiments. 22 illustrates a block diagram of another memory circuit according to some embodiments. 23 and 24 Illustrative circuit diagrams based on the block diagram of 18 are configured according to some embodiments. DETAILED DESCRIPTION The following disclosure provides many different embodiments, or examples, for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first structural element over or on top of a second structural element in the following description may include embodiments in which the first and second structural elements are formed in direct contact, and may also include embodiments in which additional structural elements may be formed between the first and second structural elements, such that the first and second structural elements might not be in direct contact. Additionally, the present disclosure may repeat reference numbers and/or letters in the various examples. This repetition serves the purpose of simplification and clarity and does not itself establish any relationship between the different embodiments and/or configurations discussed. Furthermore, spatially relative terms such as "underlying", "below", "under", "overlying", "above", "above", "below", and the like may be used herein to facilitate description and to describe the relationship of one element or structural element to another element(s) or structural element(s), as illustrated in the figures. These spatially relative terms are intended to encompass various orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be oriented differently (rotated by 90 degrees or in other orientations), and the spatially relative descriptive terms used herein may be