DE-102025112329-A1 - Semiconductor structure with back-side contacting and method for its formation

DE102025112329A1DE 102025112329 A1DE102025112329 A1DE 102025112329A1DE-102025112329-A1

Abstract

One method of the present disclosure comprises forming a stack on a substrate, structuring the stack and the substrate to form a first and second active region, forming an insulating structure between the first and second active regions, depositing an insulating structure protective layer on the insulating structure, forming a dummy gate stack over the first and second active regions, deepening the first and second active regions to form a first and second trench, forming a first and second source/drain structural element in the first and second trench, removing the dummy gate stack to form a gate trench, depositing a gate structure in the gate trench that forms an interface with the insulating structure protective layer, thinning the substrate and the insulating structure, forming a backside opening that exposes a bottom surface of the first source/drain structural element, and forming a backside via in the backside opening and in electrical coupling with the first source/drain structural element. Source/Drain structural element.

Inventors

Yu-Chun Lin
Po-Yu Huang
Chen-Ming Lee
I-Wen Wu
Mei-Yun Wang

Assignees

TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Dates

Publication Date: 20260513
Application Date: 20250331
Priority Date: 20250321

Claims (20)

Method comprising: Forming a stack on a substrate, the stack having multiple channel layers nested with multiple sacrificial layers; Structuring the stack and the substrate to form a first region and a second region extending longitudinally in a first direction, the first region having a first active region and a first basal region, and the second region having a second active region and a second basal region; Forming an isolation structure between the first basal region and the second basal region, the isolation structure forming an interface with a side wall of the first basal region and a side wall of the second basal region; Depositing an isolation structure protection layer on the isolation structure; Forming a dummy gate stack over the first active region and the second active region, the dummy gate stack forming an interface with a cover surface of the isolation structure protection layer; Depositing gate spacers on side walls of the dummy gate stack; Deepening the first and second active areas outside the dummy gate stack and gate spacers to form a first and second trench, respectively; forming a first source/drain structure element in the first trench and a second source/drain structure element in the second trench, wherein a portion of the first source/drain structure element hangs over the isolation structure along a second direction different from the first, and a portion of the second source/drain structure element hangs over the isolation structure along the second direction; Removing the dummy gate stack to form a gate trench, the gate trench exposing the isolation structure protection layer; Removing the sacrificial layers from the gate trench; Depositing a gate structure in the gate trench, the gate structure forming an interface with the top surface of the isolation structure protection layer; Thinning the substrate and the isolation structure; Forming a rear opening that exposes a bottom surface of the first source/drain structural element; and forming a rear through-hole connection in the rear opening and in electrical coupling with the first source/drain structural element.
Procedure according to Claim 1 , whereby the thinning exposes a base area of the insulation structure protection layer.
Procedure according to Claim 1 , whereby the thinning process completely removes the insulating structure.
Procedure according to one of the Claims 1 until 3 , wherein the insulation structure contains an oxide and the insulation structure protection layer contains a nitride.
Procedure according to one of the Claims 1 until 4 , wherein a section of the insulation structure protection layer between the first and second base region is etched through before the formation of the first and second source/drain structural elements.
Procedure according to Claim 5 , further comprising: Deposition of an intermediate dielectric layer over the first and second source/drain structural element, wherein a lower section of the intermediate dielectric layer extends below a bottom surface of the insulation structure protection layer.
Procedure according to one of the Claims 1 until 6 , wherein the removal of the dummy gate stack forms a pit on the insulation structure protection layer, such that a lower section of the gate structure lies in the pit under a cover surface of the insulation structure protection layer.
Procedure according to one of the Claims 1 until 7 , further comprising: before forming the first and second source/drain structural elements, forming a first epitaxial buffer layer in the first trench and a second epitaxial buffer layer in the second trench, with thinning exposing the first epitaxial buffer layer.
Procedure according to one of the Claims 1 until 8 , wherein, between the first and second base area, a cover surface of the insulation structure protection layer has a dishing profile.
Procedure according to Claim 9 , wherein an edge of the dishing profile forms an interface with a side wall of one of the lowest sacrificial layers.
Method comprising: providing a structure with a front and a back, wherein the structure has a substrate at the back of the structure and a fin-shaped structure at the front of the structure; forming an insulating structure on the sidewalls of the fin-shaped structure; forming an insulating structure protective layer on the insulating structure; epitaxially growing a source/drain structural element on the fin-shaped structure; depositing a contact etch stop layer over the source/drain structural element; Deposition of a first intermediate dielectric layer over the contact etch stop layer; deposition of a cover layer over a cover surface of the contact etch stop layer and a cover surface of the first intermediate dielectric layer; deposition of a second intermediate dielectric layer over the cover layer, wherein the thickness of the first intermediate dielectric layer is greater than the thickness of the second intermediate dielectric layer; formation of a source/drain contact plug located in the first intermediate dielectric layer for electrical coupling to the source/drain structural element; formation of a metal silicide layer located between the source/drain structural element and the source/drain contact plug, wherein the electrical conductivity of the metal silicide layer is between that of the source/drain structural element and that of the source/drain contact plug, and wherein the metal silicide layer has a curved profile; thinning of the structure from the back side of the structure until the insulation structure protection layer is exposed; Forming an opening that exposes a bottom surface of the source/drain structural element; and depositing a backside via in the opening.
Procedure according to Claim 11 , whereby thinning the structure also exposes the first interdielectric layer from the back of the structure.
Procedure according to Claim 11 or 12 , more comprehensively: Formation of an undoped epitaxial layer beneath the source/drain structural element, whereby thinning of the structure also exposes the undoped epitaxial layer.
Procedure according to one of the Claims 11 until 13 , further comprising: forming a dummy gate stack over the fin-shaped structure; replacing the dummy gate stack with a metal gate structure, wherein the metal gate structure forms an interface with a cover surface of the insulating structure protection layer; and forming a dielectric structural element that divides the metal gate structure, wherein thinning the structure also exposes the dielectric structural element.
Procedure according to one of the Claims 11 until 14 , with the thickness of the insulation structure protection layer ranging from about 10 nm to about 50 nm.
Procedure according to one of the Claims 11 until 15 , more comprehensively: prior to the epitaxial growth of the source/drain structural element, etching through the insulation structure protection layer.
Semiconductor structure comprising: a first and a second source/drain structural element; one or more nanostructures connecting the first and second source/drain structural elements; a gate structure engaging with the one or more nanostructures, the gate structure comprising a gate dielectric layer and a gate electrode layer over the gate dielectric layer; a gate spacer extending along a side wall of the gate structure, the dielectric constant of the gate dielectric layer being greater than the dielectric constant of the gate spacer; an intermediate dielectric layer arranged over the first and second source/drain structural elements; a source/drain contact extending through the intermediate dielectric layer for electrical coupling to the first source/drain structural element, the electrical conductivity of the source/drain contact being greater than the electrical conductivity of the first source/drain structural element; a protective layer located beneath a base surface of the gate structure and forming an interface with it, wherein a base surface of the intermediate dielectric layer and a base surface of the protective layer are coplanar; a backside dielectric layer located on the base surface of the protective layer; a metal conductor embedded in the backside dielectric layer; and a backside via directly beneath the first source/drain structural element, electrically connecting the metal conductor to the first source/drain structural element.
Semiconductor structure according to Claim 17 , wherein the bottom surface of the gate structure lies beneath a top surface of the protective layer.
Semiconductor structure according to Claim 17 or 18 , whereby the protective layer prevents the gate structure from forming an interface with the rear dielectric layer.
Semiconductor structure according to one of the Claims 17 until 19 , wherein a cover surface of the metal conduit forms an interface with the base surface of the interdielectric layer.

Description

PRIORITY DATA This application claims priority of the provisional US patent application no. 63/719,403 , submitted on November 12, 2024, which is incorporated into the present application by reference. BACKGROUND The integrated semiconductor (semiconductor) circuitry industry has experienced exponential growth. Technological advances in IC materials and design have produced generations of ICs, each with smaller and more complex circuits than the previous one. During IC development, functional density (i.e., the number of interconnected devices per unit area of the chip) has generally increased, while geometric size (i.e., the smallest component (or trace) that can be produced using a manufacturing process) has decreased. This downward scaling process generally offers advantages by increasing production efficiency and reducing associated costs. However, such downward scaling has also increased the complexity of machining and manufacturing ICs. ICs are typically stacked, with transistors at the bottom layer and interconnects (vias and wires) on top of them to connect to the transistors. Power rails (such as metal traces for voltage sources and ground planes) are also located above the transistors and can be part of the interconnect structure. As ICs become smaller, so do the power rails, which can lead to increased voltage drop across the rails and higher current consumption. Signal traces can also be affected by this miniaturization, such as the decreasing signal line spacing, which can lead to increased parasitic capacitance and reduced switching speed. While existing approaches in semiconductor manufacturing are generally suitable for their intended purpose, they are not entirely satisfactory. One area of interest is the creation of lower-profile vias on the back of an IC to reduce resistance. BRIEF DESCRIPTION OF THE DRAWINGS The present disclosure is best understood with reference to the following detailed description in conjunction with the accompanying drawings. It is emphasized that, in accordance with industry practice, various features are not shown to scale and are used for illustrative purposes only. In fact, the dimensions of the various features may have been arbitrarily enlarged or reduced for the sake of clarity. 1 illustrates a flowchart of a method for forming a semiconductor device according to one or more aspects of the present disclosure. 2 illustrates a perspective view of a structure under development (WIP structure, work-in-progress) according to one or more aspects of the present disclosure. 3-43 illustrate fragmentary top and cross-sectional views of the WIP structure during a manufacturing process according to the method of 1 according to one or more aspects of the present revelation. 44-46 Illustrating fragmentary cross-sectional views of an alternative embodiment of the WIP structure during a manufacturing process according to the method of 1 according to one or more aspects of the present revelation. DETAILED DESCRIPTION The following disclosure provides many different embodiments, or examples, for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first structural element over or on top of a second structural element in the following description may include embodiments in which the first and second structural elements are formed in direct contact, and may also include embodiments in which additional structural elements may be formed between the first and second structural elements, such that the first and second structural elements might not be in direct contact. Additionally, the present disclosure may repeat reference numbers and/or letters in the various examples. This repetition serves the purpose of simplification and clarity and does not itself establish any relationship between the different embodiments and/or configurations discussed. Furthermore, spatially relative terms such as "underlying", "below", "under", "overlying", "above", and the like may be used herein to facilitate description and to describe the relationship of one element or structural element to another element(s) or structural element(s), as illustrated in the figures. These spatially relative terms are intended to encompass various orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be oriented differently (rotated by 90 degrees or in other orientations), and the spatially relative descriptive terms used herein may be interpreted accordingly. Furthermore, when a number or range of numbers is described using terms like "approximately," "about," or similar, the term encompasses numbers that lie within a reasonable range, taking into account variations that naturally occur during manufacturing, as understood by a person sk