DE-102025112617-A1 - FORMATION OF CFETS THROUGH LOW-TEMPERATURE NEW GROWTH

Abstract

One method comprises forming a lower transistor and an upper transistor above the lower transistor. The lower transistor has a lower source/drain region above a semiconductor substrate, and the lower source/drain region has a bottom surface facing the semiconductor substrate. The upper transistor has an upper source/drain region positioned above the lower source/drain region. The method further comprises forming a contact opening to expose the bottom surface of the lower source/drain region, performing an epitaxial process to grow a semiconductor layer on the lower source/drain region, and forming a silicide layer electrically connected to the lower source/drain region by the semiconductor layer. By regrowing low-temperature epitaxial semiconductor layers from the back surface of the source/drain regions, the resistance of the lower source/drain regions and the corresponding contact resistance are reduced. By applying low-temperature epitaxy to form the source/drain regions, the resistance of the source/drain regions and the corresponding contact terminals is reduced.

Inventors

• Che Chi Shih
• Cheng-Wei Liu
• Wei-De Ho
• Ji-Yin Tsai
• Ku-Feng Yang
• Pei-Ren Jeng
• Szuya Liao

Assignees

• TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Dates

Publication Date

20260513

Application Date

20250401

Priority Date

20250324

Claims (20)

1. A method comprising: Forming a lower transistor, comprising: Forming a lower source/drain region over a semiconductor substrate, wherein the lower source/drain region has a bottom surface facing the semiconductor substrate; Forming an upper transistor, comprising: Forming an upper source/drain region over the lower source/drain region; Thinning the semiconductor substrate; Forming a contact opening to expose the bottom surface of the lower source/drain region; Performing a first epitaxial growth process to grow a first semiconductor layer on the lower source/drain region; and Forming a silicide layer, wherein the silicide layer is electrically connected to the lower source/drain region through the first semiconductor layer.
2. Procedure according to Claim 1 , furthermore, comprehensive execution of a second epitaxy process to grow a second semiconductor layer over the first semiconductor layer.
3. Procedure according to Claim 2 , wherein the silicide layer is formed by silicifying a section of the second semiconductor layer.
4. Procedure according to Claim 2 , wherein the first semiconductor layer and the second semiconductor layer contain germanium.
5. Procedure according to Claim 4 , wherein the second semiconductor layer has a higher atomic percentage of germanium than the first semiconductor layer.
6. Procedure according to one of the Claims 1 until 5 , wherein the lower source/drain region is formed at a first temperature, and the first epitaxy process is carried out at a second temperature, which is lower than the first temperature.
7. Procedure according to one of the Claims 1 until 6 , further comprising: forming an additional silicide layer at the lower source/drain region, wherein the silicide layer and the additional silicide layer are arranged on opposite sides of the lower source/drain region; and forming a contact terminal which contacts the additional silicide layer, wherein the contact terminal penetrates the upper source/drain region.
8. Procedure according to one of the Claims 1 until 7 , furthermore comprising forming a contact opening from a rear side of the lower source/drain region, wherein the first semiconductor layer is formed in the contact opening.
9. A method comprising: Forming a first transistor having a first source/drain region, wherein the first source/drain region is arranged over a semiconductor substrate; Performing a backside thinning process to thin the semiconductor substrate; Forming a contact opening from a backside of the semiconductor substrate, thereby exposing a rear face of the first source/drain region; Depositing a first semiconductor layer over the rear face of the first source/drain region; Depositing a second semiconductor layer over the first semiconductor layer; Silicideting the second semiconductor layer to form a silicide layer; and Forming a backside contact connection linking the silicide layer.
10. Procedure according to Claim 9 , where both the first source/drain region and the first semiconductor layer contain silicon germanium.
11. Procedure according to Claim 10 , wherein the first semiconductor layer has a higher atomic percentage of germanium than the first source/drain region.
12. Procedure according to Claim 11 , wherein the second semiconductor layer contains germanium and is essentially free of silicon.
13. Procedure according to one of the Claims 9 until 12 , wherein the first source/drain region is formed at a first temperature, and the first semiconductor layer and the second semiconductor layer are formed at a second temperature, which is lower than the first temperature.
14. Procedure according to one of the Claims 9 until 13 , wherein the first semiconductor layer and the second semiconductor layer are applied by selective epitaxy.
15. Procedure according to one of the Claims 9 until 14 , furthermore comprising: forming a second transistor which has a second source/drain region, wherein the second source/drain region overlaps the first source/drain region.
16. Procedure according to Claim 15 , where the first transistor and the second transistor together form a complementary field-effect transistor.
17. Structure comprising: a lower transistor comprising a lower source/drain region, the lower source/drain region comprising: a semiconductor region; and a first semiconductor layer located below the semiconductor region; a first silicide layer located below the semiconductor region and electrically connected to it by the first semiconductor layer; a contact etch stop layer comprising: a lower portion located below the semiconductor region; and a sidewall section contacting a sidewall of the semiconductor region, the first semiconductor layer being lower than the sidewall section of the contact etch stop layer; and a first contact terminal located below and connected to the first silicide layer.
18. Structure according to Claim 17 , further comprising: a second semiconductor layer between the first semiconductor layer and the first silicide layer.
19. Structure according to Claim 17 or 18 , further comprising: a second silicide layer above and in contact with the semiconductor area; and a second contact terminal which is arranged above and connected to the second silicide layer.
20. Structure according to one of the Claims 17 until 19 , further comprising: an upper transistor which has an upper source/drain area which overlaps the lower source/drain area.

Description

PRIORITY CLAIM AND CROSS-REFERENCE This patent application claims priority over the following provisionally filed US patent application: Application number 63/718,011 , filed on November 8, 2024, entitled “Semiconductor Device and Method for Fabricating the Same”, which is incorporated into the present application by reference. BACKGROUND Semiconductor devices are used in a wide variety of electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. Semiconductor devices are typically fabricated by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor layers onto a semiconductor substrate and structuring the various material layers using lithography to create circuit components and elements on them. By continuously reducing the minimum feature size, which allows more components to be integrated into a given area, the semiconductor industry is constantly improving the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.). However, reducing the minimum feature size introduces additional problems that need to be addressed. BRIEF DESCRIPTION OF THE DRAWINGS Aspects of this disclosure are best understood with reference to the following detailed description in conjunction with the accompanying figures. It should be noted that, in accordance with industry practice, various elements are not shown to scale. In fact, the dimensions of various features or elements may have been arbitrarily enlarged or reduced for the sake of clarity. 1 presents a perspective view of an exemplary complementary field-effect transistor (CFET) in accordance with some embodiments. The 2 - 6, 7A, 7B and 8 - 16 These are views of intermediate stages in the manufacture of CFETs in accordance with some embodiments. 17 represents a process flow for manufacturing the CFETs in 16 in accordance with some embodiments. The 18 - 37 These are views of intermediate stages in the manufacture of CFETs in accordance with some embodiments. 38 represents a process flow for manufacturing the CFETs in 37 in accordance with some embodiments. DETAILED DESCRIPTION The following disclosure provides numerous different embodiments, or examples, for implementing various features/elements of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, only examples and are not to be considered as limitations. For example, the formation of a first element above or on top of a second element in the following description may include embodiments in which the first and second elements are in direct contact with each other, but may also include embodiments in which additional elements may be formed between the first and second elements such that the first and second elements are not in direct contact with each other. Furthermore, the present disclosure may repeat reference numerals and/or reference numerals in the various examples. This repetition serves the purpose of simplification and clarity and does not, in itself, prescribe a relationship between the various embodiments and/or configurations discussed. Furthermore, terms of spatial relationships, such as "underlying," "below," "lower," "above," "upper," and the like, may be used herein for a simpler description of the relationship of one element or feature to another element(s) or feature(s) shown in the figures. These spatial relationship terms serve to encompass various other orientations of the device during its use or operation, in addition to the orientation depicted in the figures. The device may be oriented differently (rotated by 90 degrees or in other orientations), and the spatial relationship terms used herein may be interpreted accordingly. Complementary field-effect transistors (CFETs) and the methods for their fabrication are provided. In accordance with some embodiments, each CFET has a lower The CFET consists of a source/drain region and an upper source/drain region that overlaps the lower source/drain region. A back-side regrowth process is initiated from the back of the CFET. Germanium-containing epitaxial layers are formed from the back of the lower source/drain region. The epitaxial process can be carried out at a low temperature to achieve a high activation rate in the lower source/drain region. In accordance with the alternative embodiments, lower dummy source/drain regions and upper dummy source/drain regions are formed. The upper dummy source/drain regions are then removed from the front side of the wafer, and upper substitute source/drain regions are formed by low-temperature epitaxy. The lower dummy source/drain regions are removed from the back side of the wafer, and lower substitute source/drain regions are formed by low-temperature epitaxy. The dummy source/drain regions facilitate the self-alignment of the low-temperature epitaxy. The low-temperature epitaxy en