Search

DE-102025112666-A1 - Memory circuits with selectively coupled sampling amplifiers on access lines and methods for operating these

DE102025112666A1DE 102025112666 A1DE102025112666 A1DE 102025112666A1DE-102025112666-A1

Abstract

A memory circuit comprises: a first memory cell configured to store a first data bit; a second memory cell configured to store a second data bit; a sampling amplifier coupled to the first and second memory cells, respectively, via a data bit line and a reference bit line; a first switch; and a second switch. The first switch is selectively coupled between the data bit line and a first input node of the sampling amplifier, and the second switch is selectively coupled between the reference bit line and a second input node of the sampling amplifier.

Inventors

  • Tung-Cheng Chang
  • Ku-Feng Lin

Assignees

  • TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Dates

Publication Date
20260513
Application Date
20250401
Priority Date
20250314

Claims (20)

  1. A memory circuit comprising: a first memory cell configured to store a first data bit, a second memory cell configured to store a second data bit, a sampling amplifier coupled to the first memory cell and the second memory cell, respectively, via a data bit line and a reference bit line, respectively, a first switch, and a second switch, where the first switch is selectively coupled between the data bit line and a first input node of the sampling amplifier, and the second switch is selectively coupled between the reference bit line and a second input node of the sampling amplifier.
  2. Memory circuit according to Claim 1 , where the first data bit represents either a logical high state or a logical low state, and the second data bit is associated with a constant logical state between the logical high state and the logical low state.
  3. Memory circuit according to Claim 1 or 2 , wherein the first and second switches each have a transmission gate, a p-transistor, or an n-transistor.
  4. Memory circuit according to one of the Claims 1 until 3 , wherein the sampling amplifier further comprises: a first p-type transistor, a second p-type transistor, a third p-type transistor, a fourth p-type transistor, a fifth n-type transistor, a sixth n-type transistor, a seventh n-type transistor, and an eighth n-type transistor.
  5. Memory circuit according to Claim 4 , wherein the first, third, fifth and seventh transistors are connected in series between a supply voltage and a ground voltage, and the second, fourth, sixth and eighth transistors are connected in series between the supply voltage and the ground voltage.
  6. Memory circuit according to Claim 5 , wherein the gate terminals of the first and seventh transistors are connected to the second input node, and the gate terminals of the second and eighth transistors are connected to the first input node.
  7. Memory circuit according to Claim 5 , wherein the gate terminals of the third and fourth transistors are configured to receive a first control signal together, and the gate terminals of the fifth and sixth transistors are configured to receive a second control signal that is logically opposite to the first control signal together.
  8. Memory circuit according to Claim 5 , wherein the first source/drain terminals of the third and fifth transistors are connected together at the first input node, and the first source/drain terminals of the fourth and sixth transistors are connected together at the second input node.
  9. Memory circuit according to Claim 5 , wherein during an evaluation phase of the sampling amplifier the third to sixth transistors are switched off, and the first, second, seventh and eighth transistors are switched on, with the first and second switches activated, thereby coupling the data bit line to the first input node and coupling the reference bit line to the second input node.
  10. Memory circuit according to Claim 5 , wherein during a latch phase of the sampling amplifier the first to eighth transistors are switched on, with the first and second switches being deactivated, thereby decoupling the first input node from the data bit line and decoupling the second input node from the reference bit line.
  11. Memory circuit according to one of the Claims 1 until 10 , wherein the first memory cell and the second memory cell each have a non-volatile memory cell.
  12. Memory circuit comprising: a sampling amplifier configured to identify a data bit stored by a first memory cell based on a comparison of a first signal present on a data bit line connecting the first memory cell to the sampling amplifier and a second signal present on a reference bit line connecting a second memory cell to the sampling amplifier, a first switch configured to selectively couple the data bit line to a first input node of the sampling amplifier based on an activation signal, and a second switch configured to selectively couple the reference bit line to a second input node of the sampling amplifier based on the activation signal.
  13. Memory circuit according to Claim 12 , wherein the first memory cell and the second memory cell each have a non-volatile memory cell.
  14. Memory circuit according to Claim 12 or 13 , where the first signal corresponds to a logical high state or a logical low state, while the second signal corresponds to a logical state between the logical high state and the logical low state.
  15. Memory circuit according to one of the Claims 12 until 14 , wherein the sampling amplifier further comprises: a first p-type transistor, a second p-type transistor, a third p-type transistor, a fourth p-type transistor, a fifth n-type transistor, a sixth n-type transistor, a seventh n-type transistor, and an eighth n-type transistor.
  16. Memory circuit according to Claim 15 , wherein the first, third, fifth and seventh transistors are connected in series between a supply voltage and a ground voltage, and the second, fourth, sixth and eighth transistors are connected in series between the supply voltage and the ground voltage.
  17. Memory circuit according to Claim 16 , wherein during an evaluation phase of the sampling amplifier the third to sixth transistors are switched off, and the first, second, seventh and eighth transistors are switched on, with the first and second switches activated, thereby coupling the data bit line to the first input node and coupling the reference bit line to the second input node.
  18. A method for operating a memory circuit, comprising: Preloading a data bitline and a reference bitline to a first logical state, wherein the data bitline and the reference bitline are each coupled to a first input node and a second input node of a sampling amplifier, respectively, wherein the data bitline is coupled to a data cell, while the reference bitline is coupled to a reference cell; Discharging the data bitline and the reference bitline, wherein the first input node and the second input node each remain coupled to the data bitline and the reference bitline, respectively, and wherein the first input node and the second input node are each decoupled from each transistor; and Intermediately storing a data bit stored by the data cell, wherein the first input node and the second input node are each decoupled from the data bitline and the reference bitline, respectively.
  19. Procedure according to Claim 18 , wherein the data cell and the reference cell each have a non-volatile memory cell.
  20. Procedure according to Claim 18 or 19 , furthermore comprising: simultaneously activating a first switch to couple the first input node to the data bit line and activating a second switch to couple the second input node to the reference bit line, or simultaneously deactivating the first switch to decouple the first input node from the data bit line and deactivating the second switch to decouple the second input node from the reference bit line.

Description

REFERENCE TO RELATED REGISTRATION This application claims priority and the benefit of preliminary proceedings. US application number 63/719,851 , which was submitted on November 13, 2024, and which is incorporated herein by reference in its entirety for all purposes. BACKGROUND The semiconductor industry has experienced rapid growth due to continuous improvements in the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.). For the most part, this improvement in integration density stems from repeated reductions in the minimum component size, allowing more components to be integrated into a given area. BRIEF DESCRIPTION OF THE DRAWINGS Aspects of this disclosure are best understood from the detailed description below, when read together with the accompanying figures. It should be noted that, in accordance with standard industry practice, various features are not drawn to scale. In fact, the dimensions of the various features may have been arbitrarily enlarged or reduced for the sake of clarity. 1 shows an example block diagram of a memory circuit, according to some embodiments. 2 shows an example circuit diagram of a memory cell of the memory circuit of 1 , according to some embodiments. 3 shows an example circuit diagram of a section of the storage circuit of 1 , according to some embodiments. 4 shows waveforms of different signals during the operation of the memory circuit. 1 , according to some embodiments. 5 , 6 and 7 Each shows example circuit diagrams of switches in the storage circuit of 1 , according to some embodiments. 8 shows another example circuit diagram of a section of the memory circuit of 1 , according to some embodiments. 9 shows an alternative circuit diagram of a sampling amplifier for the storage circuit of 1 , according to some embodiments. 10 shows another alternative circuit diagram of a sampling amplifier for the storage circuit of 1 , according to some embodiments. 11 shows an example flowchart of a procedure for operating the memory circuit of 1 , according to some embodiments. DETAILED DESCRIPTION The following disclosure provides many different embodiments, or examples, for implementing various features of the present subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, forming a first element over or on top of a second element in the following description may include embodiments in which the first and second elements are in direct contact, and may also include embodiments in which additional elements may be formed between the first and second elements, so that the first and second elements may not be in direct contact. Furthermore, the present disclosure may repeat reference numbers and/or letters in the various examples. This repetition is done for the sake of simplicity and clarity and does not, in itself, prescribe a relationship between the various embodiments and/or configurations discussed. Furthermore, terms relating to spatial relativity, such as "below," "under," "lower," "above," "upper," "above," "below," and the like, may be used herein for the convenience of discussion to describe the relationship of one element or feature to another element or feature (or other elements or features), as illustrated in the figures. The terms relating to spatial relativity are intended to encompass various orientations of the apparatus used or operated in addition to the orientation illustrated in the figures. The apparatus may be oriented in a different way (rotated by 90 degrees or otherwise), and the terms relating to spatial relativity used herein may likewise be interpreted accordingly. Many modern electronic devices have electronic storage devices set up for storing data. An electronic storage device is typically either volatile or non-volatile. A volatile storage device retains data while powered, while a non-volatile storage device retains data even when power is lost. A resistive random-access memory (RRAM) device is a promising candidate for next-generation non-volatile memory technology. RRAM devices feature a simple structure, a small cell area, low switching voltage and fast switching times, and compatibility with CMOS (complementary metal-oxide semiconductor) fabrication processes. The RRAM device features a variable-resistance dielectric layer sandwiched between conductive electrodes and is designed to operate based on a reversible switching process between resistance states. This reversible switching is achieved by selectively forming a conductive filament through the variable-resistance dielectric layer. For example, the normally insulating variable-resistance dielectric layer can be made conductive by applying a voltage across the conductive electrodes to form a conductive filament extending through the layer. An RRAM cell can have a first resistance state