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DE-102025114055-A1 - DOUBLE-POLY BATCH CELL FOR NON-VOID MEMORY

DE102025114055A1DE 102025114055 A1DE102025114055 A1DE 102025114055A1DE-102025114055-A1

Abstract

A non-volatile memory bit cell (NVM bit cell) is disclosed. The NVM bit cell includes a control gate, a state transistor, and an access transistor coupled in series with the state transistor. The control gate includes a floating terminal formed by a first polysilicon layer, a control terminal formed by a second polysilicon layer, and a control gate dielectric layer formed between the first and second polysilicon layers, the control gate dielectric being a high-k dielectric layer. The state transistor includes a floating gate terminal formed by the first polysilicon layer and coupled to the floating terminal of the control gate. The state transistor further includes a tunnel oxide layer formed between the first polysilicon layer and an active area of the state transistor.

Inventors

  • Gang Liu
  • Santosh Menon
  • Adam Peter Cosmin
  • Bruce Blair GREENWOOD

Assignees

  • SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Dates

Publication Date
20260513
Application Date
20250409
Priority Date
20241111

Claims (20)

  1. Non-volatile memory bit cell (NVM bit cell), comprising: a control gate, comprising: a floating terminal formed by a first polysilicon layer; a control terminal formed by a second polysilicon layer; and a control gate dielectric layer formed between the first polysilicon layer and the second polysilicon layer, the control gate dielectric layer including a high-k dielectric layer; a state transistor, comprising: a floating gate terminal formed by the first polysilicon layer and coupled to the floating terminal of the control gate; and a tunnel oxide layer formed between the first polysilicon layer and an active area of the state transistor; and an access transistor coupled in series with the state transistor.
  2. NVM bit cell after Claim 1 , further comprising: a basin area in which the state transistor and the access transistor are formed; and a trench area with a trench depth that is greater than or equal to a basin depth of the basin area.
  3. NVM bit cell after Claim 2 , where: the well region is a p-well region; and the state transistor and the access transistor are NMOS transistors.
  4. NVM bit cell after Claim 2 , wherein: the tub area is located in a deep tub; and the tub area has a conductivity type opposite to that of the deep tub.
  5. NVM bit cell after Claim 1 , where the state transistor and the control gate are configured together to use Fowler-Nordheim tunnels for an erase operation and a write operation.
  6. NVM bit cell after Claim 1 , wherein the control gate dielectric layer further includes at least one silicon dioxide layer.
  7. NVM bit cell after Claim 1 , wherein the control gate dielectric layer further includes a first silicon dioxide layer on a first side of the high-K dielectric layer and a second silicon dioxide layer on a second side of the high-K dielectric layer.
  8. Integrated circuit comprising: a logic block; and a non-volatile memory bit cell array (NVM bit cell array) coupled to the logic block, the NVM bit cell array comprising a plurality of NVM bit cells arranged in multiple rows and multiple columns, each NVM bit cell comprising: a control gate comprising: a floating terminal formed by a first polysilicon layer; a control terminal formed by a second polysilicon layer; and a control gate dielectric layer formed between the first polysilicon layer and the second polysilicon layer, the control gate dielectric layer including a high-k dielectric layer; a state transistor comprising: a floating gate terminal formed by the first polysilicon layer and coupled to the floating terminal of the control gate; and a tunnel oxide layer formed between the first polysilicon layer and an active area of the state transistor; and an access transistor coupled in series with the state transistor.
  9. Integrated circuit according to Claim 8 , wherein each NVM bit cell further comprises: a well region in which the state transistor and the access transistor are formed; and a trench region with a trench depth greater than or equal to a well depth of the well region.
  10. Integrated circuit according to Claim 9 , where: the well region is a p-well region; and the state transistor and the access transistor are NMOS transistors.
  11. Integrated circuit according to Claim 9 , wherein: the tub area is located in a deep tub; and the tub area has a conductivity type opposite to that of the deep tub.
  12. Integrated circuit according to Claim 9 , where the basin area is shared by a first NVM bit cell and one or more adjacent NVM bit cells located in the same column.
  13. Integrated circuit according to Claim 9 , where the basin area of a first NVM bit cell is isolated by the trench area from the trough area of an adjacent NVM bit cell arranged in the same row.
  14. Integrated circuit according to Claim 8 , where the state transistor and the control gate are configured together to use Fowler-Nordheim tunnels for an erase operation and a write operation.
  15. Integrated circuit according to Claim 8 , wherein the control gate dielectric layer further includes at least one silicon dioxide layer.
  16. Integrated circuit according to Claim 8 , wherein the control gate dielectric layer further includes a first silicon dioxide layer on a first side of the high-K dielectric layer and a second silicon dioxide layer on a second side of the high-K dielectric layer.
  17. Method comprising: Forming a well region; Forming an access transistor in the well region; Forming a state transistor in the well region, wherein the state transistor has a floating-gate terminal formed by a first polysilicon layer; Forming a control gate with a floating terminal formed by the first polysilicon layer, a control terminal formed by a second polysilicon layer, and a control gate dielectric layer arranged between the first and second polysilicon layers and enclosing a high-k dielectric layer.
  18. Procedure according to Claim 17 , furthermore encompassing the formation of a trench area that borders the basin area on at least one side and has a trench depth that is greater than or equal to the basin depth of the basin area.
  19. Procedure according to Claim 17 , wherein the control gate dielectric layer is formed with a first silicon dioxide layer on a first side of the high-K dielectric layer and a second silicon dioxide layer on a second side of the high-K dielectric layer.
  20. Procedure according to Claim 17 , where the state transistor and the control gate are configured together to use Fowler-Nordheim tunnels for an erase operation and a write operation.

Description

TECHNICAL AREA The disclosure relates generally to the technology of integrated circuits and in particular to the design and manufacturing process of a non-volatile storage device. BACKGROUND Integrated circuits can be designed to include both a data processing unit, such as a central processing unit or a graphics processing unit, and a memory block that can be used to store data for use by the data processing unit. In some configurations, the memory block may include non-volatile memory (NVM), such as electrically erasable programmable read-only memory (EEPROM). Conventional technologies for embedding non-volatile memory in the same complementary metal-oxide-semiconductor (CMOS) integrated circuit as a data processing unit utilize the gate oxide of the CMOS process to instantiate a logic-based single-poly EEPROM with a floating gate. The inventors of embodiments of the present disclosure recognized that such embedded single-poly EEPROM cells typically require control gate and floating gate transistors, separated by an access transistor and a state transistor, as well as their isolation. In this context, the inventors of embodiments of the present disclosure also recognized that the footprint of such embedded single-poly EEPROM cells is typically large, thus occupying a significant area of the semiconductor chip. Other multi-polylayer NVM technologies have been developed with a smaller footprint than single-poly EEPROM cells. However, the inventors of the embodiments of the present disclosure recognized that such other NVM technologies are disadvantageously associated with higher process costs and lower reliability. Embodiments of the present disclosure can overcome one or more of these problems. BRIEF DESCRIPTION OF THE DRAWINGS A more comprehensive understanding of the present embodiments can be obtained by referring to the following description in conjunction with the accompanying drawings, in which the same reference numerals refer to the same elements. 1 illustrates a block diagram of an integrated circuit according to embodiments of the present disclosure. 2 illustrates a schematic diagram of a bit cell for non-volatile memory according to embodiments of the present disclosure. 3 is a diagram illustrating the operating conditions of a bit cell for non-volatile memory according to embodiments of the present disclosure. 4 illustrates a top view of semiconductor process areas for a bit cell array for non-volatile memory according to embodiments of the present disclosure. 5A Figure 1 illustrates a cross-sectional view of an array of bit cells for non-volatile memory according to embodiments of the present disclosure. 5B Figure 1 illustrates a cross-sectional view of an array of bit cells for non-volatile memory according to embodiments of the present disclosure. 5C Figure 1 illustrates a cross-sectional view of an array of bit cells for non-volatile memory according to embodiments of the present disclosure. 6 is a diagram illustrating the operating conditions of a bit cell for non-volatile memory according to embodiments of the present disclosure. 7 This illustrates a method for manufacturing a bit cell for non-volatile memory according to embodiments of the present disclosure. DETAILED DESCRIPTION Details of one or more embodiments are set forth in the following description and the accompanying drawings. Other features will become apparent from the description, the drawings, and the claims. 1 Figure 1 illustrates a block diagram of an integrated circuit 100 according to embodiments of the present disclosure. The integrated circuit 100 can include a logic block 101, a non-volatile memory bit cell array (NVM bit cell array) 102, a programming unit 104, an erase unit 106, and a read unit 108. Logic block 101 can include a data processing unit, such as a central processing unit or a graphics processing unit. The NVM bit cell array 102 can comprise a plurality of NVM bit cells, which are divided into several The logic block 101 can be coupled to the NVM bit cell array 102 and can use the NVM bit cell array 102 to store information that can be used in one or more data processing functions. Programming unit 104, erase unit 106, and read unit 108 can be configured to provide the NVM bit cell array 102 with the respective voltages for programming, erasing, and reading bit cells within the NVM bit cell array 102. As shown in 1 As shown, in some embodiments the programming unit 104, erase unit 106, and read unit 108 can be implemented as separate units. In other embodiments, the programming unit 104, erase unit 106, and read unit 108 can be implemented together in a single circuit, for example, with a charge pump and one or more voltage dividers that can be used together to generate the respective different voltages that can be used to program, erase, and read one or more bit cells of the NVM bit cell array 102. 2 Figure 1 illustrates a schematic diagram of a bit cell 200 of a non-volatile memory (NVM) according to