Search

DE-102025135921-A1 - Threshold voltage adjustment using a multi-dipole loop process for monolithic CFET devices

DE102025135921A1DE 102025135921 A1DE102025135921 A1DE 102025135921A1DE-102025135921-A1

Abstract

The present disclosure provides a method comprising: providing a substrate; generating active regions on the substrate, wherein the active regions contain a plurality of first and second semiconductor layers stacked alternately; fabricating a dielectric gate layer on the active regions; fabricating a first dipole material M, which is patterned on the dielectric gate layer of upper and lower field-effect transistors (FETs); performing a first dipole process on the dielectric gate layer at a first temperature T1; fabricating a second dipole material X on the dielectric gate layer of the upper FETs, but not on the dielectric gate layer of the lower FETs, wherein X is different from M; performing a second dipole process on the dielectric gate layer at a second temperature T2, which is lower than T1; and depositing a work-function metal material on the dielectric gate layer of the lower and upper FETs.

Inventors

  • Cheng-Ming Lin
  • Tsung-Kai CHIU
  • Wei-Yen Woon
  • Szuya Liao

Assignees

  • TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Dates

Publication Date
20260513
Application Date
20250908
Priority Date
20250411

Claims (20)

  1. A method comprising: Providing a substrate; Producing active regions on the substrate, wherein the active regions are designed for field-effect transistors (FETs) with different threshold voltages and the active regions contain a plurality of first semiconductor layers of a first semiconductor material and second semiconductor layers of a second semiconductor material, stacked alternately, the second semiconductor material having a different composition than the first semiconductor material; Producing a dielectric gate layer on the active regions; Producing a first dipole material M, which is patterned on the dielectric gate layer of upper FETs and lower FETs; Performing a first dipole process on the dielectric gate layer at a first temperature T1; Producing a second dipole material X on the dielectric gate layer of the upper FETs, but not on the dielectric gate layer of the lower FETs, wherein X is different from M; Performing a second dipole process on the dielectric gate layer with a second temperature T2 that is lower than T1; and applying a work-function metal material to the dielectric gate layer of the lower FETs and the upper FETs.
  2. Procedure according to Claim 1 , where the lower FETs are p-FETs (PFETs) and the upper FETs are n-FETs (NFETs) stacked vertically on top of the PFETs.
  3. Procedure according to Claim 1 or 2 , where: the first dipole material M comprises a first n-dipole material, the second dipole material X comprises a second n-dipole material, and the work function metal material comprises a p-work function metal.
  4. Procedure according to Claim 3 , wherein: the first n-dipole material comprises lanthanum oxide, yttrium oxide, erbium, scandium oxide, lanthanum nitride, yttrium nitride, erbium nitride, scandium nitride, lanthanum carbide, yttrium carbide, erbium carbide, scandium carbide or a combination thereof, and the second n-dipole material comprises strontium oxide, magnesium oxide, strontium nitride, magnesium nitride, strontium carbide, magnesium carbide or a combination thereof.
  5. Procedure according to Claim 3 or 4 , wherein the p-work function metal material comprises titanium nitride (TiN), tantalum nitride (TaN), ruthenium (Ru), molybdenum (Mo), tungsten (W), platinum (Pt), titanium (Ti), aluminum (Al), tantalum carbide (TaC), tantalum carbonitride (TaCN), tantalum silicon nitride (TaSiN), titanium silicon nitride (TiSiN), other suitable materials or combinations thereof.
  6. Method according to any of the preceding claims, wherein: the first dipole material M comprises a first p-dipole material, the second dipole material X comprises a second p-dipole material, and the work function metal material comprises an n-work function metal.
  7. Procedure according to Claim 6 , wherein: the first p-dipole material comprises aluminium oxide, vanadium oxide, ruthenium oxide, rhodium oxide, rhenium oxide, osmium oxide, iridium (Ir), aluminium nitride, vanadium nitride, ruthenium nitride, rhodium nitride, rhenium nitride, osmium nitride, iridium oxide, oxide, aluminium carbide, vanadium carbide, ruthenium carbide, rhodium carbide, rhenium carbide, osmium carbide, iridium carbide or a combination thereof, and the second p-dipole material comprises titanium oxide, zinc oxide, indium oxide, gallium oxide, tantalum oxide, tungsten oxide, titanium nitride, zinc nitride, indium nitride, gallium nitride, tantalum nitride, tungsten nitride, titanium carbide, zinc carbide, indium carbide, gallium carbide, tantalum carbide, tungsten carbide or a combination thereof.
  8. Procedure according to Claim 6 or 7 , wherein the n exit work metal is tantalum (Ta), titanium aluminum (TiAl), titanium aluminum carbide (TiAlC), titanium aluminum oxide (TiAlO), titanium aluminum nitride (TiAlN) or a combination thereof.
  9. A method according to any of the preceding claims, further comprising producing a filler metal on the exit work metal material, wherein the filler metal comprises copper (Cu), tungsten (W), cobalt (Co), ruthenium (Ru), other suitable conductive materials or combinations thereof.
  10. Method according to any of the preceding claims, wherein T1 is higher than 700 °C and T2 is lower than 500 °C.
  11. Method comprising: providing a substrate; generating active regions on the substrate, wherein the active regions are designed for field-effect transistors (FETs) with different threshold voltages and the active regions comprise a plurality of first semiconductor layers made of a first semiconductor material and of second semiconductor layers made of a second semiconductor material comprising alternating stacks of semiconductor materials, the second having a different composition than the first; fabricating a dielectric gate layer on the active regions; fabricating a first dipole material M, which is patterned on the dielectric gate layer of upper and lower FETs; performing a first dipole process on the dielectric gate layer at a first temperature T1; fabricating a second dipole material X on the dielectric gate layer of the upper FETs, wherein X is different from M; performing a second dipole process on the dielectric gate layer at a second temperature T2, which is lower than T1; and depositing a work-function metal material on the dielectric gate layer of the lower and upper FETs, wherein the lower FETs comprise FETs of the first type and the upper FETs comprise FETs of the second type, which are opposite to the FETs of the first type.
  12. Procedure according to Claim 11 , where T1 is higher than 700 °C and T2 is lower than 500 °C.
  13. Procedure according to Claim 11 or 12 , where the lower FETs are p-FETs (PFETs) and the upper FETs are n-FETs (NFETs) stacked vertically on top of the PFETs.
  14. Procedure according to one of the Claims 11 until 13 , where: the first dipole material M comprises a first n-dipole material, the second dipole material X comprises a second n-dipole material, and the work function metal material comprises a p-work function metal.
  15. Procedure according to Claim 14 , wherein: the first n-dipole material comprises lanthanum oxide, yttrium oxide, erbium, scandium oxide, lanthanum nitride, yttrium nitride, erbium nitride, scandium nitride, lanthanum carbide, yttrium carbide, erbium carbide, scandium carbide or a combination thereof, the second n-dipole material comprises strontium oxide, magnesium oxide, strontium nitride, magnesium nitride, strontium carbide, magnesium carbide or a combination thereof, and the p-workflow metal comprises titanium nitride (TiN), tantalum nitride (TaN), ruthenium (Ru), molybdenum (Mo), tungsten (W), platinum (Pt), titanium (Ti), aluminum (Al), tantalum carbide (TaC), tantalum carbonitride (TaCN), tantalum silicon nitride (TaSiN), titanium silicon nitride (TiSiN), other suitable materials or combinations thereof.
  16. Procedure according to one of the Claims 11 until 13 , where: the first dipole material M comprises a first p-dipole material, the second dipole material X comprises a second p-dipole material, and the work function metal material comprises an n-work function metal.
  17. Procedure according to Claim 16 , wherein: the first p-dipole material comprises aluminum oxide, vanadium oxide, ruthenium oxide, rhodium oxide, rhenium oxide, osmium oxide, iridium (Ir), aluminum nitride, vanadium nitride, ruthenium nitride, rhodium nitride, rhenium nitride, osmium nitride, iridium oxide, oxide, aluminum carbide, vanadium carbide, ruthenium carbide, rhodium carbide, rhenium carbide, osmium carbide, iridium carbide or a combination thereof, the second p-dipole material comprises titanium oxide, zinc oxide, indium oxide, gallium oxide, tantalum oxide, tungsten oxide, titanium nitride, zinc nitride, indium nitride, gallium nitride, tantalum nitride, tungsten nitride, titanium carbide, zinc carbide, indium carbide, gallium carbide, tantalum carbide, tungsten carbide or a combination thereof, and the n-work metal is tantalum (Ta), titanium-aluminum (TiAl), titanium aluminum carbide (TiAlC), titanium aluminum oxide (TiAlO), titanium aluminum nitride (TiAlN) or a combination thereof.
  18. Semiconductor device comprising: a first complementary metal oxide semiconductor (CFET) comprising a first n-field-effect transistor (NFET) and a first p-field-effect transistor (PFET) directly beneath the first NFET, wherein the first NFET comprises a first NFET channel and a first dielectric NFET gate layer surrounding the first NFET channel, and the first PFET comprises a first PFET channel and a first dielectric PFET gate layer surrounding the first PFET channel; and a gate metal electrode directly on the first dielectric NFET gate layer and the first dielectric PFET gate layer, wherein: the first dielectric NFET gate layer contains a first n-dipole dotande with a first concentration and a second n-dipole dotande, and the first dielectric PFET gate layer contains neither the first n-dipole dotande nor the second n-dipole dotande.
  19. Semiconductor device according to Claim 18 , which further comprises: a second CFET, which has a second NFET and a second PFET directly below the second NFET, wherein the second NFET has a second NFET channel and a second dielectric NFET gate layer around the second NFET channel, and the second PFET has a second PFET channel and a second dielectric PFET gate layer around the second PFET channel comprising; and a third CFET comprising a third NFET and a third PFET directly below the third NFET, wherein the third NFET comprises a third NFET channel and a third dielectric NFET gate layer surrounding the second NFET channel, and the third PFET comprises a third PFET channel and a third dielectric PFET gate layer surrounding the third PFET channel, wherein: the gate metal electrode is arranged directly on the second and third dielectric NFET gate layers and the second and third dielectric PFET gate layers, the second dielectric NFET gate layer contains the first n-dipole dotande with a second concentration, while the third dielectric NFET gate layer does not contain the first n-dipole dotande, and the first, second, and third dielectric NFET gate layers each contain the second n-dipole dotande with the same concentration, and the second dielectric PFET gate layer contains the first The third dielectric PFET gate layer contains the first n-dipole dotande with a third concentration, while the second and third dielectric PFET gate layers do not contain the second n-dipole dotande.
  20. Semiconductor device according to Claim 18 or 19 , further comprising a p-workout metal contacting the first, second and third dielectric NFET gate layer and the first, second and third dielectric PFET gate layer, wherein: the p-workout metal comprises titanium nitride (TiN), tantalum nitride (TaN), ruthenium (Ru), molybdenum (Mo), tungsten (W), platinum (Pt), titanium (Ti), aluminum (Al), tantalum carbide (TaC), tantalum carbonitride (TaCN), tantalum silicon nitride (TaSiN), titanium silicon nitride (TiSiN), other suitable materials or combinations thereof, the first comprising n-dipole dopant containing lanthanum oxide, and the second comprising n-dipole dopant containing strontium oxide.

Description

priority claim The present application claims priority over the preliminary US patent application filed on November 13, 2024, under file number 63/719,867 , which is incorporated into the present application by reference. background The present disclosure relates to an IC structure (IC: integrated circuit) and a method for its fabrication. In particular, the IC structure comprises a transistor structure with multiple vertically stacked gate-all-around transistors, each having multiple vertically stacked nanowires or nanosheets as channels. Furthermore, the IC structure includes a CFET structure (CFET: complementary metal-oxide semiconductor), and a method for fabricating the CFET is provided. The CFET can have n-FETs vertically stacked over p-FETs or p-FETs vertically stacked over n-FETs. For advanced technologies such as CFETs, devices with multiple threshold voltages (Vt) are required to provide devices with high speed and low standby power. Existing structures and methods use different metal gate thicknesses or materials to generate multiple Vt values. However, due to the scaling of critical dimensions, relying on metal gate thickness and different metallic materials becomes difficult in advanced technologies. The existing threshold voltage adjustment for IC devices is generally suitable for its intended purposes, but it is not yet satisfactory in every respect. Brief description of the drawings Aspects of the present disclosure are best understood with reference to the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with industry practice, various features are not shown to scale. Rather, the dimensions of the various features may have been arbitrarily enlarged or reduced for the sake of clarity. It is also emphasized that the accompanying drawings merely represent typical embodiments of the present invention and therefore should not be considered as limiting the scope of protection, since the invention may apply equally to other embodiments. 1 shows a sectional view of a CFET structure with multiple Vt values, according to various aspects of the present disclosure. 2A shows a perspective representation of the CFET structure, in whole or in part, according to various aspects of the present disclosure. 2B shows a sectional view of the CFET structure, in whole or in part, according to various aspects of the present disclosure. The 3A and 3B include a flowchart of a method for manufacturing a CFET semiconductor device with multiple Vt values, in whole or in part, according to various aspects of the present disclosure. The 4 to 12 show sectional views of an IC structure with multiple Vt values at intermediate stages of manufacturing processes according to the method of 3A and 3B according to one embodiment of the present disclosure. 13 is a flowchart of a process for fabricating a CFET semiconductor structure with multiple Vt values, fully or partially, according to various aspects of the present disclosure. The 14A to 14G show sectional views of the CFET semiconductor structure at intermediate stages of manufacturing processes according to some embodiments of the present disclosure. The 15A and 15B show tables with different dipole compositions and concentrations in dielectric gate layers of lower and upper FETs according to an embodiment of the present disclosure. The 16A and 16B show diagrams of distributions of different dipole compositions and concentrations in dielectric gate layers of lower and upper FETs according to an embodiment of the present disclosure. The 17A to 17C show partial sectional views of a CFET semiconductor structure manufactured according to some embodiments of the present disclosure. Detailed description The disclosure below provides many different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to illustrate the present disclosure. To simplify matters, these are of course merely examples and are not intended to be limiting. For example, the fabrication of a first element over or on a second element in the following description may include embodiments in which the first and second elements are fabricated in direct contact, and it may also include embodiments in which additional elements can be fabricated between the first and second elements, so that the first and second elements are not in direct contact. Furthermore, reference numerals and/or letters may be repeated in the various examples in this disclosure. This repetition serves for simplicity and clarity and does not in itself prescribe a relationship between the various embodiments and/or configurations discussed. Furthermore, spatially relative terms, such as "located below," "under," "lower," "located above," "upper," and the like, can be used here to simply describe the relationship of one element or structural element to one or more other eleme