DE-102025144223-A1 - METHOD AND DEVICES FOR TRACKING AN OSCILLATOR FREQUENCY USING DIGITAL FILTERS

DE102025144223A1DE 102025144223 A1DE102025144223 A1DE 102025144223A1DE-102025144223-A1

Abstract

An exemplary setup includes the following: a first oscillator circuit arrangement; a second oscillator circuit arrangement; a period calculator circuit arrangement coupled to the first oscillator circuit arrangement and the second oscillator circuit arrangement; an averaging circuit arrangement coupled to the period calculator circuit arrangement; and a coefficient filter circuit arrangement coupled to the averaging circuit arrangement.

Inventors

Anurag Choudhury
Robin Hoel
Torjus Kallerud
Ashutosh Mishra

Assignees

TEXAS INSTRUMENTS INCORPORATED

Dates

Publication Date: 20260513
Application Date: 20251029
Priority Date: 20241113

Claims (20)

A device comprising: a first oscillator circuit arrangement; a second oscillator circuit arrangement; a period calculator circuit arrangement coupled to the first oscillator circuit arrangement and coupled to the second oscillator circuit arrangement; an averaging circuit arrangement coupled to the period calculator circuit arrangement; and a coefficient filter circuit arrangement coupled to the averaging circuit arrangement.
establishment according Claim 1 , further comprising a multiplexer circuit arrangement comprising: a first input coupled to the period calculator circuit arrangement; a second input coupled to the averaging circuit arrangement; and an output coupled to the coefficient filter circuit arrangement.
establishment according Claim 2 , wherein the averaging circuit arrangement includes an input that is coupled to the period calculator circuit arrangement and is coupled to the first input of the multiplexer circuit arrangement.
establishment according Claim 1 , further comprising a noise detection circuit arrangement comprising: a first input coupled to the averaging circuit arrangement; a second input coupled to the coefficient filter circuit arrangement; and an output coupled to the second input of the coefficient filter circuit arrangement.
establishment according Claim 4 , wherein the noise detection circuit arrangement comprises: a detection threshold circuit arrangement; a combination circuit arrangement coupled to the averaging circuit arrangement and coupled to the coefficient filter circuit arrangement; and a comparator circuit arrangement coupled to the detection threshold circuit arrangement, coupled to the combination circuit arrangement, coupled to the averaging circuit arrangement, and coupled to the coefficient filter circuit arrangement.
establishment according Claim 5 , wherein the combination circuit arrangement is designed to generate an error value based on a difference between a first value received from the averaging circuit arrangement and a second value received from the coefficient filter circuit arrangement, and wherein the comparator circuit arrangement is designed to: receive a threshold value from the detection threshold circuit arrangement; and compare the error value with the threshold value.
establishment according Claim 1 , wherein the period calculator circuit arrangement is designed to generate a value based on a ratio of the following: a frequency of the first oscillator circuit arrangement; and a frequency of the second oscillator circuit arrangement.
establishment according Claim 1 , further comprising a real-time clock (RTC) accumulator circuit arrangement coupled to the first oscillator circuit arrangement and coupled to the coefficient filter circuit arrangement.
establishment according Claim 8 , further comprising: a programmable circuit arrangement coupled to the RTC accumulator circuit arrangement; and an interface circuit arrangement coupled to the programmable circuit arrangement.
establishment according Claim 1 , further comprising: a coefficient circuit arrangement coupled to the coefficient filter circuit arrangement; and a programmable circuit arrangement coupled to the period calculator circuit arrangement, coupled to the averaging circuit arrangement and coupled to the coefficient circuit arrangement.
A device comprising: a period calculator circuit arrangement including an output; a smoothing circuit arrangement including an output coupled to the output of the period calculator circuit arrangement; a noise detection circuit arrangement coupled to the output of the smoothing circuit arrangement; and a coefficient filter circuit arrangement coupled to the noise detection circuit arrangement.
establishment according Claim 11 , wherein the coefficient filter circuit arrangement is coupled to the output of the averaging circuit arrangement.
establishment according Claim 11 , wherein the coefficient filter circuit arrangement includes an output coupled to the noise detection circuit arrangement, and wherein the noise detection circuit arrangement includes an output coupled to the coefficient filter circuit arrangement.
establishment according Claim 11 , wherein the noise detection circuit arrangement comprises: a detection threshold circuit arrangement; a combination circuit arrangement coupled to the averaging circuit arrangement and coupled to the coefficient filter circuit arrangement; and a comparator circuit arrangement coupled to the detection threshold circuit arrangement, coupled to the combination circuit arrangement, coupled to the averaging circuit arrangement, and coupled to the coefficient filter circuit arrangement.
establishment according Claim 14 , wherein the combination circuit arrangement is designed to generate an error value based on a difference between a first value received from the averaging circuit arrangement and a second value received from the coefficient filter circuit arrangement, and wherein the comparator circuit arrangement is designed to: receive a threshold value from the detection threshold circuit arrangement; and compare the error value with the threshold value.
establishment according Claim 11 , further comprising: a coefficient circuit arrangement coupled to the coefficient filter circuit arrangement; and a programmable circuit arrangement coupled to the period calculator circuit arrangement, coupled to the averaging circuit arrangement and coupled to the coefficient circuit arrangement.
establishment according Claim 11 , further comprising: a first oscillator circuit arrangement coupled to the period calculator circuit arrangement; a second oscillator circuit arrangement coupled to the period calculator circuit arrangement; a real-time clock (RTC) accumulator circuit arrangement; and a clock control circuit arrangement coupled to the coefficient filter circuit arrangement, the first oscillator circuit arrangement, the second oscillator circuit arrangement, and the RTC accumulator circuit arrangement, wherein the clock control circuit arrangement is designed to: determine whether the device is in a standby mode; if not in standby mode, increment a value of the RTC accumulator circuit arrangement based on the first oscillator circuit arrangement; and When in standby mode, the value of the RTC accumulator circuit arrangement is incremented by one count of the coefficient filter circuit arrangement.
A device comprising: a period calculator circuit arrangement designed to determine the number of cycles of a first signal in one period of a second signal; an averaging circuit arrangement coupled to the period calculator circuit arrangement and designed to determine the average number of cycles of the first signal in a plurality of periods of the second signal; and a coefficient filter circuit arrangement coupled to the averaging circuit arrangement and designed to filter the average number of cycles of the first signal based on a filter coefficient.
establishment according Claim 18 , further comprising a noise detection circuit arrangement coupled to the averaging circuit arrangement and the coefficient filter circuit arrangement, wherein the noise detection circuit arrangement is designed to: determine a count difference between an average of the number of cycles and a filtered number of cycles from the coefficient filter circuit arrangement; and detect random telegraph noise based on a comparison of the count difference with a threshold count.
establishment according Claim 19 , wherein the noise detection circuit arrangement is further designed to set an initial value of the coefficient filter circuit arrangement to the mean value of the number of cycles based on a detection of random telegraph noise.

Description

TECHNICAL AREA This description generally concerns frequency tracking and, in particular, methods and equipment for tracking an oscillator frequency using digital filters. BACKGROUND Oscillator circuits generate a periodic signal capable of sequencing increasingly advanced operations. In some systems, the counting cycles of an oscillator signal provide a real-time clock (RTC) counter that represents the passage of time. In communication systems, oscillator signals provide a basis for initiating and conducting wireless communications. Oscillator circuits control an increasing number of operations over an increasingly wide range of operating conditions. SUMMARY For methods and devices for tracking an oscillator frequency with digital filters, an exemplary device includes a first oscillator circuit arrangement; a second oscillator circuit arrangement; a period calculator circuit arrangement coupled to the first and second oscillator circuit arrangements; an averaging circuit arrangement coupled to the period calculator circuit arrangement; and a coefficient filter circuit arrangement coupled to the averaging circuit arrangement. Other examples are described. For methods and devices for tracking an oscillator frequency using digital filters, an exemplary device includes a period calculator circuit arrangement including an output; an averaging circuit arrangement including an output coupled to the output of the period calculator circuit arrangement; a noise detection circuit arrangement coupled to the output of the averaging circuit arrangement; and a coefficient filter circuit arrangement coupled to the noise detection circuit arrangement. Other examples are described. For methods and devices for tracking an oscillator frequency using digital filters, an exemplary device includes a period calculator circuit arrangement designed to determine the number of cycles of a first signal in one period of a second signal; an averaging circuit arrangement coupled to the period calculator circuit arrangement designed to determine the average number of cycles of the first signal in a plurality of periods of the second signal; and a coefficient filter circuit arrangement coupled to the averaging circuit arrangement designed to filter the average number of cycles of the first signal based on a filter coefficient. Other examples are described. BRIEF DESCRIPTION OF THE DRAWINGS 1 is a block diagram of an exemplary system-on-chip (SoC) that includes an exemplary frequency tracking circuit arrangement.2 This is a block diagram of an example of the frequency tracking circuit arrangement of 1 , which includes an exemplary averaging circuit arrangement and an exemplary coefficient filter circuit arrangement.3 is a block diagram of a first filter operating mode of the frequency tracking circuit arrangement of 1 and 2 , which the averaging circuit arrangement of 2 and the coefficient filter circuit arrangement of 2 includes.4 is a block diagram of a second filter operating mode of the frequency tracking circuit arrangement of 1 , 2 and 3 , which the averaging circuit arrangement of 2 and 3 and the coefficient filter circuit arrangement of 2 and 3 includes.5A and 5B form a flowchart representing exemplary machine-readable instructions or exemplary operations that can be performed using an exemplary implementation of the frequency tracking circuit arrangement of 1 , 2 , 3 and 4 or more generally, the SoC of 1 can be executed, instantiated and/or carried out.6 is a timing diagram of exemplary operations of the averaging circuit arrangement of 2 , 3 and 4 and the coefficient filter circuit arrangement of 2 , 3 and 4 .7 is a plot of exemplary operations of the frequency tracking circuit arrangement of 1 , 2 , 3 and 4 .8 is a block diagram of an exemplary processing platform that includes a programmable circuit arrangement used to execute, instantiate, or perform the exemplary machine-readable instructions sung or performing the exemplary operations of 5A and 5B is structured to accommodate the frequency tracking circuit arrangement 115, 200, 300, 400 of 1 , 2 , 3 and 4 to implement.9 is a block diagram of an exemplary implementation of the programmable circuit arrangement of 8 .10 is a block diagram of another exemplary implementation of the programmable circuit arrangement of 8 . The drawings are not necessarily to scale. Generally, the same reference numbers in one or more drawings and in this description refer to the same or (functionally and/or structurally) similar features and/or parts. Although the drawings show areas with distinct lines and boundaries, some or all of these lines and boundaries may be idealized. In reality, the boundaries or lines may be unobservable, blended into one another, or irregular. DETAILED DESCRIPTION Oscillator circuits generate a periodic signal that can be used to sequence advanced operations. In some systems, accumulating a count of oscillator cycles provides a real-time clock (RTC) count that represen