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DE-102025144247-A1 - SINGLE-PIN IMPEDANCE MEASURING SYSTEM AND PHASE SHIFT COMPENSATION FOR A SINGLE-PIN IMPEDANCE MEASURING SYSTEM

DE102025144247A1DE 102025144247 A1DE102025144247 A1DE 102025144247A1DE-102025144247-A1

Abstract

An impedance measurement system comprising: a signal generator incorporating a memory and configured to generate a digital test signal and at least one digital demodulation signal based on the memory, wherein the digital test signal has a first frequency and the at least one digital demodulation signal has the first frequency; a single pin for supplying an analog test signal based on the digital test signal to a device under test (DUT) and for measuring an analog input signal in response to the supply of the analog test signal to the DUT; and a demodulator configured to obtain: a first filtered digital signal based on the input signal; and the at least one digital demodulation signal to generate at least one digital demodulated signal indicating the impedance.

Inventors

  • Norbert Greitschus
  • Thomas Schürmann

Assignees

  • RENESAS ELECTRONICS AMERICA INC.

Dates

Publication Date
20260513
Application Date
20251029
Priority Date
20241111

Claims (20)

  1. An impedance measurement system comprising: a signal generator including a memory and configured to generate a digital test signal and at least one digital demodulation signal based on the memory, wherein the digital test signal has a first frequency and the at least one digital demodulation signal has the first frequency; a single pin for supplying an analog test signal based on the digital test signal to a device under test (DUT) and for measuring an analog input signal in response to the supply of the analog test signal to the DUT; and a demodulator configured to obtain: a first filtered digital signal based on the input signal; and the at least one digital demodulation signal, to generate at least one digital demodulated signal indicating the impedance.
  2. Impedance measurement system according to Claim 1 , wherein the at least one demodulation signal comprises a first sinusoidal signal and a second sinusoidal signal, the second sinusoidal signal being generated by phase shifting the first sinusoidal signal by 90 degrees.
  3. Impedance measurement system according to Claim 1 , further comprising an input processing stage coupled to the single pin and the demodulator and configured to receive the analog input signal and to generate the first filtered digital signal based on the analog input signal.
  4. Impedance measurement system according to Claim 3 , wherein the input processing stage includes an oversampling ADC configured to generate a digital input signal based on the analog input signal.
  5. Impedance measurement system according to Claim 4 , where the oversampling ADC is a 1-bit sigma-delta ADC operating at a system frequency fs.
  6. Impedance measurement system according to Claim 4 , wherein the input processing stage includes a filter configured to filter the digital input to filter the input signal in order to generate the first filtered digital signal.
  7. Impedance measurement system according to Claim 4 , wherein the input processing stage includes an amplifier configured to provide an amplified version of the analog input signal to the oversampling ADC.
  8. Impedance measurement system according to Claim 4 , wherein the demodulator comprises an I/Q demodulator coupled to an output of the oversampling ADC, the I/Q demodulator being configured to: multiply the first filtered digital signal by the first sinusoidal signal to generate a real component signal indicating a real component of the analog input signal; and multiply the first filtered digital signal by the second sinusoidal signal to generate an imaginary component signal indicating an imaginary component of the analog input signal, wherein the at least one digital demodulated signal is based on the real component signal and/or the imaginary component signal.
  9. Impedance measurement system according to Claim 8 , further comprising an integrator coupled to the output of the I/Q demodulator, wherein the integrator comprises a frequency response with a notch at a frequency of at least one harmonic of the at least one demodulated signal, wherein the integrator is configured to filter the real component signal and the imaginary component signal to generate the at least one digital demodulated signal.
  10. Impedance measurement system according to Claim 1 , further comprising a digital-to-analog converter (DAC) coupled to the signal generator to obtain the digital test signal and to generate at least one analog test signal.
  11. Impedance measurement system according to Claim 10 , where the DAC has a sampling rate that is less than a system frequency fs.
  12. Impedance measurement system according to Claim 11 , wherein the at least one analog test signal has a frequency determined by a fraction of the system frequency f s multiplied by a prime number.
  13. Impedance measurement system according to Claim 12 , wherein the DAC is coupled to one or more filters and/or one or more buffers configured to receive an output from the DAC and to generate at least one analog test signal.
  14. Impedance measurement system according to Claim 1 , wherein the memory includes a lookup table, LUT, which stores a set of predefined values at respective memory addresses for generating the digital test signal and the at least one digital demodulation signal.
  15. Impedance measurement system .after Claim 14 , wherein the signal generator is configured to adjust the phase of the at least one digital demodulation signal and/or the digital test signal in order to correct a phase shift between the first filtered digital signal and the at least one digital demodulation signal.
  16. Impedance measurement system according to Claim 15 , wherein the signal generator sets the phase of the at least one digital demodulation signal and/or the digital test signal by adding an address offset to a part of the LUT that generated the at least one digital demodulation signal and/or the digital test signal.
  17. Impedance measurement system according to Claim 16 , where the signal generator is configured to obtain the address offset from an external system to the impedance measurement system.
  18. Impedance measurement system according to Claim 16 , which is further configured to determine the address offset during a calibration phase, wherein the calibration phase includes coupling a DUT comprising only a capacitive load to the single pin.
  19. Impedance measurement system according to Claim 16 , wherein the memory includes a set of predefined address offset values for respective temperature values.
  20. Impedance measurement system according to Claim 1 , wherein the single pin is coupled to one or more sensors integrated into a steering wheel for a vehicle, wherein the impedance measurement system is configured to drive the one or more sensors to detect the contact of an operator with the steering wheel.

Description

CROSS-REFERENCE TO RELATED REGISTRATION This application claims priority under 35 U.S.C. 9119 of British patent application No. 2416584,7, filed on November 11, 2024. The entire disclosure of British patent application No. 2416584,7 is incorporated by this reference. AREA OF INVENTION The present disclosure relates to a single-pin impedance measurement system and a phase shift compensation for a single-pin impedance measurement system, in particular, but without limitation, to a single-pin impedance measurement system comprising a phase shift compensator configured to introduce an address shift to compensate for an unknown phase shift. The single-pin impedance measurement system can be used with a steering device for a vehicle to implement a gesture-based human-machine interface system. DESCRIPTION OF THE STATE OF THE ART To measure or calculate the impedance of an external device under test (DUT), a system can generate measurements representing the amplitude and phase (or real and imaginary parts) of the impedance. To reduce the number of signal pins, only one connection per DUT should be used to provide a "test signal" to the DUT and to measure the results. A voltage can be applied to a device under test (DUT), and the system can determine the DUT's impedance by measuring the amplitude and phase of the current flowing through the DUT. Alternatively, a current can be applied to the DUT, and then the voltage across it can be measured to determine the amplitude and phase of the voltage signal. In order to measure the real and imaginary parts of a signal influenced by a complex DUT, the test signal must be a time-varying signal, for example a signal pulse or a sinusoidal wave. Typically, a sine wave is used because it has both an amplitude and a phase (real and imaginary part: "Re" & "Im"). Known systems typically implement an I/Q demodulator to derive Re and Im. The amplitude and phase of the current are measured by demodulating the signal measured at the DUT (either the current through the DUT or the voltage across the DUT) using the I/Q demodulator. This measurement is performed by multiplying the measured signal by a sine wave and a cosine wave of the same frequency. The output of the I/Q demodulator (after filtering) results in an in-phase quadrature signal at DC. The output is complex and includes a real component and an imaginary component. The amplitude is then determined by Re2+Im2 given and the phase is through arctan(JmRe) given. Known systems have limited sensitivity, making them more susceptible to noise and interference, thus reducing the accuracy and reliability of the measurement results. Furthermore, due to internal signal delays, which can be caused either by the frequency-dependent signal processing of the analog amplifiers (similar to a filter function) used in the systems that measure impedance, or by propagation delay in the digital processing, a phase shift unrelated to the device under test (DUT) can be introduced. For example, delays are introduced by mixed-signal devices such as analog-to-digital converters, which are consistent with the signal processing path. Therefore, the output of the I/Q demodulator may exhibit a phase shift unrelated to the DUT. The objective of this disclosure is to provide a single-pin impedance measurement system for measuring the impedance of an external device under test (DUT), which exhibits increased sensitivity and thus reduced noise susceptibility and increased measurement accuracy. Furthermore, it is desirable to develop a system that can account for phase shift, since correcting for phase shift improves accuracy. SUMMARY According to a first aspect of the disclosure, an impedance measurement system is provided, comprising a signal generator which includes a memory and is arranged to generate a digital test signal and at least one digital demodulation signal based on the memory, wherein the digital test signal has a first frequency and the at least one digital demodulation signal has the first frequency, a single pin for providing an analog a device under test (DUT) for sending test signals based on the digital test signal and measuring an analog input signal in response to the provision of the analog test signal to the DUT, a demodulator configured to obtain a first filtered digital signal based on the input signal and the at least one digital demodulation signal in order to generate at least one digital demodulated signal indicating the impedance. According to a second aspect of the disclosure, a single-pin impedance measurement system is provided, comprising: an oversampling analog-to-digital converter; a digital demodulator coupled to the analog-to-digital converter; and a memory configured to generate a test signal and one or more demodulation signals; wherein the test signal and the one or more demodulation signals are coherent, such that the single-pin impedance measurement system can perform a phase measurement and an amplitude measurement of