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DE-102025144536-A1 - Semiconductor device and method for manufacturing the same

DE102025144536A1DE 102025144536 A1DE102025144536 A1DE 102025144536A1DE-102025144536-A1

Abstract

A gate electrode is formed in a trench. An insulating film is formed on the gate electrode to project from the top surface of a semiconductor substrate. A sidewall spacer is formed on a side surface of the insulating film and on the top surface of the semiconductor substrate. A hole is formed in a section of the semiconductor substrate exposed by the insulating film and the sidewall spacer. A barrier metal film is formed in the hole. A second opening width of the hole at a second position, corresponding to a transition surface between a body region and a source region, is larger than a first opening width of the hole at a first position, corresponding to a position on the top surface of the semiconductor substrate. The barrier metal film comprises a silicide film and a metal film.

Inventors

  • Yukio Maki

Assignees

  • RENESAS ELECTRONICS CORPORATION

Dates

Publication Date
20260513
Application Date
20251030
Priority Date
20241112

Claims (16)

  1. Semiconductor device comprising: a semiconductor substrate of a first conductivity type with an upper surface; a trench formed in the semiconductor substrate to reach a predetermined depth from the upper surface of the semiconductor substrate; a gate electrode formed in the trench; an insulating film formed on the gate electrode to project from the upper surface of the semiconductor substrate; a body region of a second conductivity type opposite to the first conductivity type, formed in a section of the semiconductor substrate exposed by the insulating film; a source region of the first conductivity type formed in the body region; a sidewall spacer formed on a side surface of the insulating film and on the upper surface of the semiconductor substrate; a hole formed in a section of the semiconductor substrate exposed by the insulating film and the sidewall spacer to penetrate the source region and reach the body region; and a barrier metal film formed in the hole, whereby an opening width of the hole at a second position on a transition surface between the body region and the source region is larger than an opening width of the hole at a first position on the upper surface of the semiconductor substrate, and whereby the barrier metal film comprises: a silicide film formed in the hole; and a second metal film formed on top of the silicide film.
  2. Semiconductor device according to Claim 1 , wherein the opening width of the hole at a fourth position of an upper surface of the barrier metal film formed over the deepest part of the hole is smaller than the opening width of the hole at the second position and larger than the opening width of the hole at the first position.
  3. Semiconductor device according to Claim 2 , wherein the thickness of the barrier metal film formed in the hole and extending from the first position to the fourth position is less than the thickness of the barrier metal film formed in the hole and extending from the fourth position to the deepest part of the hole.
  4. Semiconductor device according to Claim 1 , wherein the barrier metal film comprises a third metal film formed in the hole to cover the second metal film and the silicide film, and wherein the thickness of the third metal film is less than the thickness of the silicide film and the thickness of the second metal film.
  5. Semiconductor device according to Claim 4 , comprising: a tungsten film formed in the hole above the barrier metal film, wherein the silicide film is a titanium silicide film, wherein the second metal film is a titanium nitride film, and wherein the third metal film is a titanium nitride film.
  6. A method for manufacturing a semiconductor device, comprising: (a) preparing a semiconductor substrate of a first conductivity type having an upper surface; (b) after (a), forming a trench in the semiconductor substrate to achieve a predetermined depth from the upper surface of the semiconductor substrate; (c) after (b), forming a gate electrode in the trench; (d) after (c), forming an insulating film in the trench and on the gate electrode; (e) after (d), performing an etching treatment on the semiconductor substrate using the insulating film as a mask to lower a position of the upper surface of the semiconductor substrate below a position of the upper surface of the insulating film; (f) after (e), forming a body region of a second conductivity type opposite to the first conductivity type in a section of the semiconductor substrate exposed by the insulating film; (g) according to (f), forming a source region of the first conductivity type in the body region; (h) according to (g), forming a sidewall spacer on a side surface of the insulating film and on the top surface of the semiconductor substrate; (i) according to (h), performing an etching treatment on the semiconductor substrate using the insulating film and the sidewall spacer as a mask to form a hole, wherein the hole penetrates the source region and reaches the body region; and (j) according to (i), forming a barrier metal film in the hole, wherein, prior to (j), an opening width of the hole at a second position of a transition surface between the body region and the source region is larger than an opening width of the hole at a first position of the top surface of the semiconductor substrate, and wherein (j) comprises: (j1) forming a first metal film in the hole using a sputtering process; (j2) following (j1), forming a second metal film on the first metal film using a sputtering process; and (j3) following (j2), performing a heat treatment to react the first metal film with silicon contained in the semiconductor substrate to form a silicide film.
  7. Procedure according to Claim 6 , where, according to (j), the opening width of the hole at the second position is larger than the opening width of the hole at the first position.
  8. Procedure according to Claim 6 , where before (j) an opening width of the hole at a third position 30 nm above the deepest part of the hole is smaller than the opening width of the hole at the second position and larger than the opening width of the hole at the first position.
  9. Procedure according to Claim 8 , wherein after (j2) and before (j3) a thickness of the barrier metal film formed in the hole and extending from the first position to the fourth position is less than a thickness of the barrier metal film formed in the hole and extending from the fourth position to the deepest part of the hole.
  10. Procedure according to Claim 6 , wherein according to (j) an opening width of the hole at a fourth position of an upper surface of the barrier metal film formed over the deepest part of the hole is smaller than the opening width of the hole at the second position and larger than the opening width of the hole at the first position.
  11. Procedure according to Claim 10 , wherein according to (j) a thickness of the barrier metal film formed in the hole and extending from the first position to the fourth position is less than a thickness of the barrier metal film formed in the hole and extending from the fourth position to the deepest part of the hole.
  12. Procedure according to Claim 6 , wherein (j) comprises: (j4) after (j3) forming a third metal film in the hole using a CVD process to cover the second metal film and the silicide film, wherein a thickness of the third metal film is less than a thickness of the silicide film and a thickness of the second metal film.
  13. Procedure according to Claim 12 , comprising: (k) forming a tungsten film in the hole over the barrier metal film using a CVD process, wherein the first metal film is a titanium film, wherein the silicide film is a titanium silicide film, wherein the second metal film is a titanium nitride film, and wherein the third metal film is a titanium nitride film.
  14. Procedure according to Claim 6 , wherein the etching treatment in (i) involves an anisotropic etching treatment using Cl 2 gas and O 2 gas, and wherein a value of “a flow rate of Cl 2 gas / a flow rate of O 2 gas” is 6 or more and 13 or less.
  15. Procedure according to Claim 14 , wherein the flow rate of the Cl 2 gas is 60 sccm or more and 80 sccm or less, and wherein the flow rate of the O 2 gas is 6 sccm or more and 10 sccm or less.
  16. Procedure according to Claim 14 , wherein the etching treatment in (i) involves an isotropic etching treatment using buffered hydrofluoric acid.

Description

CROSS-REFERENCE TO RELATED REGISTRATIONS The Revelation of Japanese patent application no. 2024-197308 , submitted on November 12, 2024, including the description, drawings and summary, is incorporated herein by reference in its entirety. BACKGROUND The present invention relates to a semiconductor device and a method for manufacturing the same, in particular a method for manufacturing a semiconductor device equipped with a gate electrode in a trench. Semiconductor devices equipped with semiconductor elements such as power MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) employ a trench-gate structure, with a gate electrode formed within the trench. A body region is formed in the semiconductor substrate located on the side face of the trench, and a source region is formed within this body region. A portion of the body region adjacent to the gate electrode via a gate insulating film functions as a channel region. In general, to electrically connect the body area and the source area to the source electrode, a hole is formed that penetrates the source area and reaches the body area. The techniques listed below will be revealed. [Patent Document 1] Japanese Disclosure Document No. 2002-246596 [Patent Document 2] Japanese Disclosure Document No. 2024-128687 For example, patent document 1 discloses a technique for forming holes in a self-aligning manner. First, a cover film made of an insulating film is formed in the trench and on the gate electrode. Next, by performing an etching treatment using the cover film as a mask, the top surface of the semiconductor substrate is deepened. As a result, the cover film protrudes from the top surface of the semiconductor substrate. Then, a body region is formed in the semiconductor substrate exposed by the cover film, and a source region is formed in the body region. Next, a sidewall spacer is formed on the side surface of the cover film. Subsequently, by performing an etching treatment using the cover film and the sidewall spacer as a mask, a hole is formed in the semiconductor substrate. Then, a high-concentration contact region is formed in the semiconductor substrate near the bottom section of the hole. Finally, a source electrode is formed on the cover film and the sidewall spacer to fill the hole. As shown in patent document 2, a technique is also known in which a plug is formed in the hole, and then a source electrode is formed to be electrically connected to the plug. The plug is formed from a laminated film comprising a barrier metal film and a conductive main film. Patent document 2 describes a laminated film comprising a metal film and a nitride metal film, which serves as the barrier metal film. The metal film is a titanium film, and the nitride metal film is a titanium nitride film. First, the metal film is formed within the hole. Next, the nitride metal film is formed on top of the metal film. Then, by reacting the metal film with the silicon contained in the semiconductor substrate through heat treatment, a silicide film is formed. Finally, a tungsten film is formed to fill the hole over this barrier metal film. SUMMARY In recent years, the miniaturization of semiconductor devices has necessitated a reduction in the hole aperture width. Consequently, when a silicide film forms on the side of the hole, it tends to form close to the channel area. Additionally, during silicide film formation, aggregation can occur within the film, and stress from the silicide film can cause cracks in the nitride metal film. These problems can reduce the reliability of the semiconductor device. Other problems and novel features will become apparent from the description in this application and the accompanying drawings. A brief overview of the typical embodiments disclosed in the present application is as follows. In one embodiment, a semiconductor device comprises a semiconductor substrate of a first conductivity type with an upper surface, a trench formed in the semiconductor substrate, a gate electrode formed in the trench, an insulating film formed on the gate electrode to project from the top surface of the semiconductor substrate, a body region of a second conductivity type opposite to the first conductivity type formed in the semiconductor substrate, a source region of the first conductivity type formed in the body region, a sidewall spacer formed on the side surface of the insulating film and on the top surface of the semiconductor substrate, a hole formed in a section of the semiconductor substrate exposed by the insulating film and the sidewall spacer to penetrate the source region and reach the body region, and a barrier metal film formed in the hole. The hole opening width at a second position, corresponding to the interface between the body region and the source region, is larger than the hole opening width at a first position, corresponding to the upper surface of the semiconductor substrate. The barrier metal film comprises a silicide film formed within th