DE-102025145304-A1 - MULTI-CHANNEL SIGNAL AND POWER ANALYST

DE102025145304A1DE 102025145304 A1DE102025145304 A1DE 102025145304A1DE-102025145304-A1

Abstract

A signal and power analysis instrument comprises one or more high-bandwidth input channels configured as one or more equivalence-time (RET) input channels and/or one or more radio frequency (RF) channels, one or more input channels configured as one or more low-bandwidth real-time (RT) input channels, one or more analog-to-digital converters (ADCs) with pipes, a first set of pipes connected to the one or more high-bandwidth input channels to generate high-bandwidth data, and a second set of pipes connected to the one or more low-bandwidth RT input channels to generate low-bandwidth RT data, a system clock connected to the high-bandwidth input channels and the low-bandwidth RT input channels, a memory connected to the system clock, the first set of pipes, and the second set of pipes, and one or more processors for storing low-bandwidth RT data and high-bandwidth data in the memory and for Matching high-bandwidth data with low-bandwidth data.

Inventors

Kan Tan

Assignees

TEKTRONIX, INC.

Dates

Publication Date: 20260513
Application Date: 20251104
Priority Date: 20251103

Claims (20)

A signal and power analysis instrument comprising: one or more high-bandwidth input channels configured as at least one of one or more equivalence-time (RET) input channels or one or more radio frequency (RF) channels connected to a device under test (DUT); one or more input channels configured as one or more low-bandwidth real-time (RT) input channels; one or more analog-to-digital converters (ADCs), each ADC having one or more pipes, a first set of the one or more pipes being connected to the one or more high-bandwidth input channels to generate high-bandwidth data, and a second set of the one or more pipes being connected to the one or more low-bandwidth RT input channels to generate low-bandwidth data; a system clock connected to the one or more high-bandwidth input channels and the one or more low-bandwidth RT input channels; a memory connected to the system clock, to the first set of one or more pipes connected to one or more high-bandwidth input channels, to the second set of one or more pipes connected to one or more low-bandwidth RT input channels; and one or more processors configured to execute code that causes the one or more processors to: store low-bandwidth data from the second set of pipes in memory; store high-bandwidth data from the first set of pipes in memory; and synchronize the high-bandwidth data and the low-bandwidth data using the system clock.
The signal and power analysis instrument according to Claim 1 , wherein the one or more high-bandwidth input channels comprise one or more RET input channels and one or more RF input channels, only RET input channels, or only RF input channels.
The signal and power analysis instrument according to Claim 1 or 2 , wherein the one or more high-bandwidth input channels further comprise one or more high-bandwidth RT input signal channels, and the instrument further comprises a third set of pipes connected to the one or more high-bandwidth RT input signal channels.
The signal and power analysis instrument according to Claim 3 , wherein the one or more high-bandwidth input channels comprise one or more RET input channels and one or more high-bandwidth RT input channels, one or more RF input channels and one or more high-bandwidth RT channels, or one or more RET input channels, one or more RF input channels and one or more high-bandwidth RT input channels.
The signal and power analysis instrument according to Claim 3 or 4 , wherein the one or more high-bandwidth input channels include one or more RET input channels, and a first set of pipes includes fewer pipes than a number of pipes in the third set of pipes.
The signal and power analysis instrument according to one of the Claims 1 until 5 , wherein one or more high-bandwidth input channels are configured to receive one or more signals from the DUT, and the high-bandwidth data includes signal data.
The signal and power analysis instrument according to Claim 6 , wherein one or more low-bandwidth RT input channels are configured to be connected to a power supply that powers the DUT, and the low-bandwidth data includes power data.
The signal and power analysis instrument according to Claim 7 , wherein the code that causes one or more processors to time-align the high-bandwidth data and the low-bandwidth data includes code to align the performance data and the signaling data using the system clock.
The signal and power analysis instrument according to one of the Claims 6 until 8 , where the signal data includes at least either RET data or RF data.
The signal and power analysis instrument according to one of the Claims 6 until 9 , where the signal data includes at least high-bandwidth RET, RF and RT data.
A method for performing a signal integrity analysis and a power integrity analysis, comprising the following: receiving one or more signals from a or multiple input channels configured as one or more low-bandwidth real-time (RT) input channels; receiving one or more signals from a device under test (DUT) via one or more high-bandwidth input channels configured as one or more equivalence-time (RET) input channels and radio frequency (RF) channels; using a first set of one or more analog-to-digital converter (ADC) pipes connected to the one or more low-bandwidth RT input channels to generate low-bandwidth RT data; using a second set of the one or more ADC pipes connected to the one or more high-bandwidth input channels to generate high-bandwidth data; storing the high-bandwidth data and the low-bandwidth real-time data in an acquisition memory; and timing-aligning the low-bandwidth RT data and the high-bandwidth data using a system clock.
The procedure according Claim 11 , wherein receiving signals from the one or more high-bandwidth input channels comprises one or more of the following steps: receiving signals from the one or more RET input channels and the one or more RF input channels, receiving signals only from the one or more RET input channels, or only from the one or more RF input channels.
The procedure according Claim 11 or 12 , which further includes receiving one or more signals from one or more high-bandwidth RT input channels and using a third set of ADC pipes connected to the one or more high-bandwidth RT input channels.
The procedure according Claim 13 , wherein receiving one or more signals from the one or more high-bandwidth input channels includes receiving one or more signals from the one or more RET input channels and the one or more high-bandwidth RT input channels, from the one or more RF input channels and the one or more high-bandwidth RT channels, or from the one or more RET input channels, from the one or more RF input channels and from the one or more high-bandwidth RT input channels.
The procedure according Claim 13 or 14 , wherein the one or more high-bandwidth input channels include one or more RET input channels, and the first set of pipes includes fewer pipes than a number of pipes in the third set of pipes.
The procedure according to one of the Claims 13 until 15 , wherein receiving one or more signals from the DUT includes receiving one or more signals from at least one of the high-bandwidth RET, RF and RT signals.
The procedure according to one of the Claims 11 until 16 , wherein receiving one or more signals from the DUT from the one or more high-bandwidth input channels includes receiving signal data.
The procedure according Claim 17 , wherein receiving one or more signals from the one or more low-bandwidth RT input channels includes receiving one or more signals from a power supply that powers the DUT, and receiving the one or more signals from the one or more low-bandwidth RT channels includes receiving power data.
The procedure according Claim 18 , where the timing alignment of the low-bandwidth data and the high-bandwidth data includes the alignment of the power data and the signal data.
The procedure according Claim 19 , which further includes performing a signal integrity analysis and a power integrity analysis on the time-aligned power and signal data.

Description

REFERENCE TO RELATED REGISTRATIONS This disclosure is a non-preliminary filing and claims precedence over the preliminary filing. US application no. 63/718,480 entitled “MULTI-CHANNEL SIGNAL AND POWER ANALYZER”, which was filed on November 8, 2024, and the disclosure of which is incorporated herein by reference in its entirety. AREA OF TECHNOLOGY This disclosure relates to test and measurement equipment, in particular a combined multi-channel signal and power analysis instrument. BACKGROUND With the advancement of generative AI, data centers, electric vehicles (EVs), 5G/6G wireless technology, and quantum computing, the need for high-channel-count instruments capable of combined signal integrity (SI) and power integrity (PI) analysis is increasing. Faster wired data transmission enables generative AI and data centers to handle the increased data demands, requiring higher performance for data transfer and processing. Industry standards such as IEEE Ethernet 800G require oscilloscopes with high analog bandwidth to measure signal integrity, while power supplies require oscilloscopes with much lower analog bandwidth to measure power integrity. Because there are correlations between signal integrity (SI) and power integrity (PI), a single instrument capable of capturing the time-correlated signals for SI/PI analysis provides users with greater insight into their designs. EV, 5G/6G radio and quantum computing all have the unmet need for a single device to capture and analyze time-correlated time-domain signals, RF signals and power supply signals. The need for such devices stems from several areas. The advancement of generative AI has triggered a significant development of high-performance computing infrastructures, including clusters of GPUs for LLM training and large data centers for data storage, processing, and transmission. These applications demand higher performance. The global adoption of electric vehicles (EVs) is increasing the need for performance analysis instruments. Modern vehicles are equipped with fast wired and wireless data communication systems to transmit video, radar, and other sensor data. Quantum computing systems are incorporating ever-increasing numbers of qubits; hundreds and thousands of qubits in a single quantum computer require spectrum analyzers with a high channel count. 5G and 6G radio testing, with their massive multi-input multi-output (MIMO) architectures, also necessitates spectrum analyzers with a higher channel count. Signal integrity analysis (SI analysis) is required for high-speed time-domain signals such as the 800G PAM4 Ethernet signal and for high-bandwidth RF signals such as 5G and 6G radio signals. Power integrity analysis (PI analysis) is required for power supplies and electric motors. The interaction between the power supply and the signal path necessitates SI/PI analysis. SI/PI analysis is initially performed during the system design phase using simulation. When the actual systems are manufactured, test equipment is used to verify the design and debug the system. The US Patent No. 11,789,051 The patent, entitled "Real-equivalent-time oscilloscope," issued on October 17, 2023, the contents of which are hereby incorporated in their entirety into this disclosure, describes a new class of oscilloscopes: real-equivalent-time (RET) oscilloscopes. The RET oscilloscope uses only a single ADC with a lower sample rate per channel, thereby significantly reducing complexity and cost compared to a conventional real-time oscilloscope, which typically has multiple ADCs time-nested to achieve a higher sample rate. US patent application no. 2024/0313795 The patent application entitled “Real-Equivalent-Time oscilloscope and Wideband Real-Time Spectrum Analyzer”, filed on February 29, 2024, the contents of which are incorporated in their entirety by reference into this disclosure, describes a new class of instruments that… US Patent No. 11,789,051 The RET oscilloscope architecture described herein is used so that the device can also be operated as a real-time spectrum analyzer. Embodiments of this disclosure utilize the architecture described herein. US Patent No. 11,789,051 and US patent application no. 2024/0313795 described technology. BRIEF DESCRIPTION OF THE DRAWINGS 1 shows an embodiment of a signal and power analysis instrument.2 shows a block diagram of an embodiment of a signal and power analysis.3 shows a block diagram of an embodiment of a channel architecture of a signal and power analysis instrument.4 shows an example of a spectrogram of a signal resulting from a power integrity problem. DETAILED DESCRIPTION The embodiments presented here include a new instrument referred to herein as the Signal and Power Analyzer (SPA). In general, the SPA has a higher channel count, its system clock enables synchronized signal acquisition across all channels, and each channel of the instrument can be configured as an oscilloscope channel with high analog bandwidth equivalent-time sam