DE-102025146266-A1 - PROGRAMMING OF ALL LEVELS WITH LOOP-DEPARATE COLUMN LIFT

Abstract

A method is provided, performed by a storage device, to perform all-level programming with loop-dependent column lifting. The method comprises, in at least one loop of a plurality of operational loops performed by a memory controller, causing a first bias to be applied to a plurality of word lines and a destination bit line. The method further comprises causing a set of ramp-up voltages to be applied to the plurality of word lines over a plurality of ramp-up periods. Each ramp-up voltage of the set of ramp-up voltages is incremented by a delta voltage in a corresponding ramp-up period of the plurality of ramp-up periods. The method further comprises identifying a destination ramp-up period for the destination memory cell. The method further comprises causing a second bias to be applied to the destination bit line during the identified destination ramp-up period.

Inventors

• Huai-Yuan Tseng
• Jeffrey S. McNeil
• Sheyang NING
• Lawrence Celso Miranda
• Tomoko Ogura Iwasaki
• Akira Goda

Assignees

• MICRON TECHNOLOGY, INC.

Dates

Publication Date

20260513

Application Date

20251110

Priority Date

20251104

Claims (10)

1. A storage device comprising: an array of memory cells including a target memory cell; a plurality of bit lines coupled to the array of memory cells, wherein the plurality of bit lines includes a target bit line coupled to the target memory cell; a plurality of word lines coupled to the array of memory cells; and a memory controller configured to perform a plurality of operation loops during a programming operation to raise a column voltage of the target memory cell, wherein in at least one loop of the plurality of operation loops the memory controller is configured to: cause an initial bias voltage to the plurality of word lines and the target bit line; cause a set of ramp voltages to be applied to the plurality of word lines over a plurality of ramp periods, wherein each ramp voltage of the set of ramp voltages is incremented by a delta voltage in a corresponding ramp period of the plurality of ramp periods; Identify a target ramp-up period for the target memory cell; and during the identified ramp-up period, cause a second bias to be applied to the target bit line.
2. Storage device according to Claim 1 , where: the time span of the second loop is greater than the time span of each of the remaining loops; the delta voltage of the first loop is less than the delta voltage of the second loop; and the delta voltage of the second loop is less than the delta voltage of each of the remaining loops.
3. Storage device according to one of the Claims 1 - 2 , where: the time span of the second loop is greater than the time span of each of the remaining loops; the set of ramp-up voltages includes an initial forward voltage; the initial forward voltage of the first loop is less than the initial forward voltage of the second loop; and the delta voltage of the first loop or the second loop is less than the delta voltage of each of the remaining loops.
4. Storage device according to one of the Claims 1 - 3 , wherein the second bias is applied after a time interval following the application of the first bias, and wherein the time interval of the second loop is greater than the time interval of each of the remaining loops; the time interval of the first loop is greater than the time interval of the second loop; and the time interval of the second loop is greater than the time interval of each of the remaining loops.
5. Storage device according to one of the Claims 1 - 4 , where the target rise period is identified such that it corresponds to a programming level of the target memory cell.
6. Storage device according to Claim 5 , wherein the plurality of operating loops comprises a first loop and a set of residual loops, and wherein the memory control is further configured to perform during the programming operation: in the first loop, identifying the target rise period such that it corresponds to a programming level higher than the programming level of the target memory cell; and in each loop of the set of residual loops, identifying the target rise period such that it corresponds to the programming level of the target memory cell.
7. Storage device according to one of the Claims 1 - 6 , wherein the memory controller is further configured to perform during the programming operation: before causing the set of rising voltages over the plurality of rise periods to be applied to the plurality of word lines, causing a drain selection gate coupled to the destination bit line to be turned on.
8. Storage device according to one of the Claims 1 - 7 , wherein the memory controller is further configured to perform during the programming operation: during the target rise period, causing a disconnection of a column connected to the target memory cell from a power supply and an electrical ground.
9. Storage device according to one of the Claims 1 - 8 , wherein the plurality of word lines comprises a set of unselected word lines coupled to other memory cells connected to the destination bit line and not being the destination memory cell, wherein the memory controller is configured to perform during the programming operation: after causing the set of rising voltages over the plurality of rise periods to be applied to the plurality of word lines, causing a pass Tension is applied to the set of unselected word lines.
10. A method that goes from the storage device to Claim 1 is performed, the method comprising a plurality of operational loops, wherein at least one of the operational loops comprises: causing a first bias to be applied to the plurality of word lines and the destination bit line; causing a set of ramp-up voltages to be applied to the plurality of word lines over a plurality of ramp-up periods, each ramp-up voltage of the set of ramp-up voltages being incremented by a delta voltage in a corresponding ramp-up period of the plurality of ramp-up periods; identifying a destination ramp-up period for the destination memory cell; and during the identified ramp-up period, causing a second bias to be applied to the destination bit line after a time interval.

Description

RELATED REGISTRATIONS This application claims priority over the provisional US application no. 63/718,864 , filed on November 11, 2024, entitled “ALL LEVELS PROGRAMMING WITH LOOP DEPENDENT PILLAR BOOSTING”, and the non-provisional US application no. 19/379,736 , submitted on November 4, 2025, entitled “ALL LEVELS PROGRAMMING WITH LOOP DEPENDENT PILLAR BOOSTING.” The contents of the provisional US application no. 63/718,864 and the non-provisional US application no. 19/379,736 are hereby incorporated by reference in their entirety for all purposes. AREA OF TECHNOLOGY This disclosure relates to one or more storage systems, including techniques for programming all levels with loop-dependent column elevation. GENERAL STATE OF THE ART Storage devices are widely used to store information in devices such as computers, user devices, wireless communication devices, cameras, digital displays, and others. Information is stored by programming memory cells within a storage device to different states. For example, binary memory cells can be programmed to one of two supported states, often referred to as logical 1 or logical 0. In some examples, a single memory cell can support more than two states, each of which can be stored. To access the stored information, the storage device can read states from the memory cells (e.g., sense, detect, retrieve, determine). To store information, the storage device can write states to the memory cells (e.g., program, set, assign). Information can also be erased from the memory cells, and new information can be stored in the memory cells. There are various types of memory devices, including magnetic disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), static RAM (SRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase-change memory (PCM), self-selecting memory, chalcogenide memory technologies, NOT-OR (NOR) and NOT-AND (NAND) memory devices, and others. Memory cells can be described as volatile or non-volatile. Memory cells configured in a non-volatile configuration can retain stored logical states for extended periods, even without an external power source. Memory cells configured in a volatile configuration can lose stored states when disconnected from an external power source. BRIEF DESCRIPTION OF THE DRAWINGS 1 is a block diagram of a storage device in communication with a storage control system of a storage system, according to the examples disclosed herein.2A-2C are illustrative diagrams of parts of an arrangement of memory cells in a storage device, according to the examples disclosed herein.3 is a block diagram of an example device for implementing one or more systems described herein and for carrying out one or more methods described herein, according to the examples disclosed herein.4A-4B illustrate a section of a three-dimensional construction of a memory cell string having a column, according to examples such as those disclosed herein.5 illustrates a set of columns corresponding to multiple programming levels in a memory arrangement, as shown in examples such herein.6 illustrates the trends of programming voltages, column potentials and effective programming voltages across loops under an all-level programming (ALP) approach, as revealed in examples such as herein.7 illustrates the trends of programming voltages, column potentials and effective programming voltages across loops under a revised ALP approach, as revealed in examples such herein.8A-8C are diagrams showing waveforms of word line and bit line biases applied to different columns, and revealing the resulting column potentials in an ALP operation according to examples such as herein.9 is a flowchart that represents a procedure for performing all-level programming with loop-dependent columnar approach The exercise is illustrated by examples such as those revealed herein. DETAILED DESCRIPTION Memory cells in storage devices can have multiple logical levels. For example, an MLC cell has 4 levels; a TLC cell has 8 levels; and a QLC cell has 16 levels. Memory cells with multiple logical levels are typically programmed one logic level at a time using a method called incremental step-pulse programming (ISPP). The ISPP method tends to use multiple programming loops to program the multiple levels of memory cells and therefore has slower programming speeds and low efficiency. All-level programming (ALP) increases the programming speed and efficiency of storage devices (such as a NAND flash memory) by allowing simultaneous programming of all levels of memory cells in a memory array, unlike ISPP. By reducing the number of programming loops, ALP speeds up the programming process, making it a more efficient method for programming high-density memory arrays compared to ISPP. However, ALP can have certain limitations. The reduced number of programming loops can result in a larger step increase in the threshold voltage (ΔVt) of the tar