DE-112016002862-B4 - Signal processing device and method for processing a signal

DE112016002862B4DE 112016002862 B4DE112016002862 B4DE 112016002862B4DE-112016002862-B4

Abstract

Signal processing device, which includes the following: a sampling time control circuit configured to provide a sequence of digital values, wherein each digital value specifies a sampling time from a sequence of sampling times, wherein the sampling time control circuit is configured to provide multiple digital values, wherein each digital value specifies an offset with respect to a respective sampling time of a predetermined grid of multiple points in time; a sampling circuit configured to sample an input signal according to the sequence of sampling times in order to generate a sample value of the input signal for each sampling time of the sequence of sampling times; a processing circuit configured to receive the sampled values and configured to process the sampled values based on the sampled times, wherein the sampled time control circuit is configured to introduce jitter into the sampled times by varying the time intervals between adjacent sampled times, and wherein the processing circuit is configured to generate further sampled values at the times of the previously specified grid of time points by interpolation, extrapolation, or both of the sampled values.

Inventors

Victor Da Fonte Dias

Assignees

APPLE INC.

Dates

Publication Date: 20260513
Application Date: 20160524
Priority Date: 20150626

Claims (20)

A signal processing device comprising: a sampling time control circuit configured to provide a sequence of digital values, wherein each digital value specifies a sample time from a sequence of sample times, and wherein the sampling time control circuit is configured to provide multiple digital values, each digital value specifying an offset with respect to a respective sample time from a predetermined grid of multiple time points; a sampling circuit configured to sample an input signal according to the sequence of sample times to generate a sample of the input signal for each sample time of the sequence of sample times; a processing circuit configured to receive the samples and configured to process the samples based on the sample times, wherein the sampling time control circuit is configured to introduce jitter into the sample times by varying the time intervals between adjacent sample times, and wherein the processing circuit is configured to generate further samples at the time points of the predetermined grid of time points by interpolation, extrapolation, or both of the samples.
Signal processing device according to Claim 1 , wherein the sampling time control circuit is configured to provide the predefined grid of multiple time points as a periodic sequence of multiple time points.
Signal processing device according to Claim 1 , wherein the sampling time control circuit is configured to provide the sampled values as samples of the amplitude of the input signal.
Signal processing device according to Claim 1 , where the sampling time control circuit is configured to determine the sequence of sampling times.
Signal processing device according to Claim 4 , wherein the sampling time control circuit is configured to determine the sequence of sampling times by varying the time intervals between adjacent sampling times based on a quality measure of the samples.
Signal processing device according to Claim 4 , wherein the processing circuit is configured to generate a digitized version of the input signal based on the sample values, and the sampling time control circuit is configured to determine the sequence of sampling times based on a quality measure of the digitized version of the input signal.
Signal processing device according to Claim 6 , wherein the sampling time control circuit is configured to provide the quality measure based on an amount of jitter in the digitized version of the input signal.
Signal processing device according to Claim 6 , wherein the sampling time control circuit is configured to provide the quality measure based on a quantity of disturbances in the digitized version of the input signal.
Signal processing device according to Claim 6 , wherein the processing circuit is configured to reconstruct transmission data from the digitized version of the input signal.
Signal processing device according to Claim 9 , wherein the sampling time control circuit is configured to receive the input signal which includes a modulated carrier signal representing the transmission data.
Signal processing device according to Claim 1 , wherein the sampling time control unit is configured to vary a time interval between two successive sampling times of the sequence of sampling times over the sequence of sampling times.
Signal processing device according to Claim 11 , wherein the processing circuit is configured to remove jitter from the samples, which is introduced by varying the time interval between two successive samples of the sequence of samples.
A method for processing a signal comprising: providing a sequence of digital values, each digital value specifying a sample time from a sequence of sample times, each digital value specifying an offset with respect to a respective sample time of a predetermined grid of multiple time points; sampling an input signal according to the sequence of sample times to generate a sample of the input signal for each sample time of the sequence of sample times; processing the sample values based on the sample times and introducing jitter into the sample times by varying the time intervals between adjacent sampling times; and that includes generating further samples at the times of the previously defined grid of times by interpolation, extrapolation or both of the samples.
Procedure according to Claim 13 , where the previously defined grid of multiple sampling times is a periodic sequence of the multiple times.
Procedure according to Claim 13 , where the sample values are samples of the amplitude of the input signal.
Procedure according to Claim 13 , which includes determining the sequence of sampling times.
Procedure according to Claim 16 , which involves determining the sequence of sampling times by varying the time intervals between adjacent sampling times based on a quality measure of the samples.
Procedure according to Claim 16 , which includes generating a digitized version of the input signal based on the sample values and determining the sequence of sampling times based on a quality measure of the digitized version of the input signal.
Procedure according to Claim 18 , where the quality measure is based on an amount of jitter in the digitized version of the input signal.
Procedure according to Claim 18 , where the quality measure is based on a quantity of disturbances in the digitized version of the input signal.

Description

Cross-reference to a related registration This application claims priority over the US patent application filed on June 26, 2015, with the number... 14/751,195 . Technical field The embodiments described herein relate generally to signal processing devices and methods for processing a signal. background Converting an analog signal to the digital domain, i.e., analog-to-digital conversion, is a typical application in communication systems, for example. An analog signal is typically sampled at a specific frequency to generate samples at regular intervals, which can then be further processed, for example, by a discrete Fourier transform. However, the samples can be affected by noise and interference, which complicates further processing. Therefore, approaches to improving the quality of the samples are desirable. The state of the art document US 9,000,809 B2 describes a method for sampling an input signal, wherein the method includes providing a single-frequency clock signal, randomly selecting clock pulses from the single-frequency clock signal to generate a spread-spectrum clock signal, and sampling the input signal using the spread-spectrum clock signal. The state of the art document US 7,424,275 B2 A system comprehensively describes a digital circuit that is clocked by a digital clock signal with an associated clock period. Summary of the invention The present invention is defined in the independent claims. Advantageous embodiments are specified in the dependent claims. Brief description of the drawings In the drawings, the same reference numerals generally denote the same parts in the different views. The drawings are not necessarily to scale, and the focus is generally on illustrating the principles of the invention. The following description describes various aspects with reference to the following drawings, in which: 1 a signal processing device is shown. 2 a flowchart that depicts a process for processing a signal. 3 a signal processing device is shown. 4 a diagram showing an example of sampling times. 5 a device, including the signal processing device. 6 A flowchart is shown that illustrates how the sampling time control circuit performs the determination of the sequence of sampling times. Description of embodiments The following detailed description refers to the accompanying drawings, which illustrate specific details and aspects of this disclosure in which the invention may be carried out. Other aspects may be used, and structural, logical, and electrical modifications may be made without deviating from the scope of protection of the invention. The various aspects of this disclosure are not necessarily mutually exclusive, because some aspects of this disclosure may be combined with one or more other aspects of this disclosure to form new aspects. Signals can be processed in a variety of domains, encompassing both continuous and discrete time and amplitude axes. For example, signals can be fully processed in the following domains: • Time-continuous and amplitude-continuous domain, which is usually referred to as the analog domain in technical language. • Time-discrete and amplitude-continuous domain, usually referred to as the sampled data domain. Implementation techniques such as switching capacitor, switching current, CCD (charge-coupled device), and others are typically used here. • Time-discrete and amplitude-discrete domain, widely known as the digital domain. A fourth combination is conceivable, as are other pseudodomains such as a sigma-delta domain, although these can be considered of minor importance for the following description. Signals in these domains can be represented in time and frequency spaces, linked by a pair of Fourier transforms. In this context, concepts such as aliasing, imaging, Nyquist rate, etc., arise. A signal can be transformed between the domains mentioned above by interface blocks such as a sampler (which discretizes time), a quantizer (which discretizes amplitude), a hold circuit (which generates a continuous-time signal from a discrete-time signal), an analog filter (which generates an amplitude-discrete signal or interpolates to generate an amplitude-continuous signal), and so on. All these interface blocks can be implemented in many variations and all correspond to specific and well-defined signal transformations in both time and frequency domains. Furthermore, a signal with either a discrete or continuous amplitude can be processed in the discrete-time domain by an interpolator or a decimator. For example, a discrete-time interpolator first generates an additional set of discrete time points between the available discrete time points; that is, it increases the rate. A discrete-time decimator removes values from a discrete-time representation of a signal; that is, it reduces the rate. Rate reducers preceded by a suitable antialiasing filter constitute a decimator, while rate increasers followed by an image removal or smoothing filter constitute an interpolator. T