DE-112017006401-B4 - METHOD FOR POLISHING A SILICON WAFER AND METHOD FOR PRODUCING A SILICON WAFER

Abstract

Method for polishing a silicon wafer (W) comprising the following: a double-sided polishing step of performing polishing on a front surface and a rear surface of a silicon wafer (W); a notched part polishing step of performing a polishing on a beveled part of a notched part (N) of the silicon wafer, while a slurry (S) is delivered to the beveled part of the notched part (N) of the silicon wafer (W), after the double-sided polishing step; a chamfered peripheral part polishing step of performing a polishing on the chamfered part on a periphery of the silicon wafer (W) except for the chamfered part of the notched part (N) after the notched part polishing step; and a high-gloss polishing step of performing high-gloss polishing on the front surface of the silicon wafer (W) after the beveled peripheral part polishing step, the notch part polishing step is carried out in a state where the front surface is wet with water.

Inventors

• Tsuyoshi Morita

Assignees

• SUMCO CORPORATION

Dates

Publication Date

20260513

Application Date

20170922

Priority Date

20161220

Claims (7)

1. A method for polishing a silicon wafer (W), comprising: a double-sided polishing step of performing polishing on a front surface and a rear surface of a silicon wafer (W); a notched-part polishing step of performing polishing on a chamfered portion of a notched part (N) of the silicon wafer while a slurry (S) is delivered to the chamfered portion of the notched part (N) of the silicon wafer (W) after the double-sided polishing step; a chamfered-peripheral-part polishing step of performing polishing on the chamfered portion on a periphery of the silicon wafer (W) other than the chamfered portion of the notched part (N) after the notched-part polishing step; and a high-gloss polishing step of performing high-gloss polishing on the front surface of the silicon wafer (W) after the chamfered peripheral part polishing step, whereby the chamfered peripheral part polishing step is performed in a condition in which the front surface is wetted with water.
2. Method for polishing a silicon wafer according to Claim 1 , wherein the water-wetted condition is achieved by subjecting the front surface to a hydrophilization process after the double-sided polishing step in order to obtain a hydrophilic surface, and supplying water to the hydrophilic surface.
3. Method for polishing a silicon wafer according to Claim 2 , where the hydrophilization process is a chemical cleaning process.
4. Method for polishing a silicon wafer according to Claim 2 or 3 , whereby the supply of water is carried out at a flow rate of 1 l/min or more and 10 l/min or less.
5. Method for polishing a silicon wafer according to Claim 1 , whereby the water-wetted condition is achieved by continuously supplying water to the front surface after the double-sided polishing step.
6. Method for polishing a silicon wafer according to one of the Claims 1 until 5 , whereby no chemical cleaning is performed between the beveled peripheral part polishing step and the high-gloss polishing step.
7. A method for producing a silicon wafer (W) comprising the steps in the following order: forming a notched portion (N) on a periphery of a single-crystal silicon ingot formed by the Czochralski process; cutting the ingot to obtain a silicon wafer (W); and subjecting the cut silicon wafer (W) to the method for polishing a silicon wafer (W) according to one of the Claims 1 until 6 .

Description

Technical field This disclosure relates to a method for polishing a silicon wafer and a method for producing a silicon wafer. background Silicon wafers are commonly used as substrates for semiconductor devices. A silicon wafer is produced as follows: First, a single-crystal silicon ingot is formed by the Czochralski (CZ) process or similar methods. Next, the periphery of the grown single-crystal silicon ingot is ground to adjust the ingot's diameter to a predetermined value. Next, a notch portion, indicating a certain crystal orientation, is formed on the peripheral surface of the single-crystal silicon ingot, which has undergone peripheral grinding. For example, a notch portion indicating, say, the <110> direction is formed in a silicon wafer where the crystal plane is the (100) plane. This notch portion is formed, for example, as a groove with an arc shape or an approximate V-shape, by moving a grinding stone in the axial direction of the ingot, with the grinding stone in contact with the ingot's periphery. Subsequently, the notched single-crystal silicon ingot is cut into blocks, a resulting single-crystal silicon block is cut using, for example, a wire saw device, and a resulting silicon wafer is subjected to chamfering, primary planarization (lapping), polishing, etc. Chamfering adapts the shape of a peripheral end part of the silicon wafer to a predefined shape using a chamfering device. This chamfering is also performed on the notched part. In primary planarization, the front surface of the silicon wafer (on which a device is manufactured) and its rear surface are subjected to coarse grinding using a lapping device, a double-disc grinding device, etc., thereby increasing the parallelism of the front and rear surfaces of the wafer. Polishing involves polishing the front and back surfaces of the silicon wafer to increase its flatness. Polishing broadly falls into two processes: double-sided polishing, which polishes both the front and back surfaces of a silicon wafer simultaneously, and single-sided polishing, which polishes only the front surface. In double-sided polishing, the front and back surfaces of a silicon wafer, loaded into a holding well of a substrate, are simultaneously polished to a desired thickness at a relatively high polishing rate using a relatively hard polishing cloth, such as one made of polyurethane. In contrast, single-sided polishing polishes the front surface of a silicon wafer using a relatively soft polishing cloth, such as suede, and fine abrasive grains, thereby reducing microsurface roughness on the silicon wafer surface, such as nanotopography or haze. The single-sided polishing, performed at the end of the process, is called fine polishing. The polishing process described above typically employs chemical-mechanical polishing (CMP), in which a slurry, obtained by adding abrasive particles (e.g., silicon oxide) to an alkaline aqueous solution, is used as a polishing agent. The silicon wafer and the polishing cloth are rotated relative to each other. The CMP process combines the mechanical polishing action of the abrasive particles with the chemical polishing action of the alkaline aqueous solution. This combined effect results in a high-gloss polish of the silicon wafer surface, achieving a high degree of flatness. Furthermore, during the polishing process described above, it is necessary to prevent the emission of particles not only from the front and back surfaces of the silicon wafer, but also from the beveled portion. Accordingly, polishing is also performed on the beveled portion at the periphery of the wafer to achieve a high-gloss finish, and polishing is carried out in the same manner on the beveled portion of the notched section. If polishing on the beveled portion of the wafer periphery is performed before double-sided polishing, the inner circumferential surface of the wafer holding hole in the carrier plate and the highly polished beveled surface will be in contact during double-sided polishing, causing scratches and thus damaging the beveled surface. To address this, performing polishing on a beveled surface after double-sided polishing was described. Polishing reported (see for example JP 2002 - 299 290 A (PTL 1)). As silicon wafers become increasingly miniaturized and integrated, it has become essential in recent years for them to have a very flat surface. Differential interference contrast (DIC) microscopy has become widely used to evaluate the flatness of such silicon wafer surfaces. DIC microscopy is a technique that allows the determination of the number of step-forming microdefects on a wafer surface. These microdefects have a raised or depressed shape with a height (or depth) exceeding a predetermined threshold (e.g., 2 nm). It is worth noting that step-forming microdefects are typically defects with a width of 30 µm to 200 µm and a height of approximately 2 nm to 90 nm, which are rarely detected using other detection methods. 1 Figure 1 is a diagram