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DE-112019007383-B4 - METHOD FOR VERIFYING THE ERASE PHASE OF A STORAGE DEVICE

DE112019007383B4DE 112019007383 B4DE112019007383 B4DE 112019007383B4DE-112019007383-B4

Abstract

A non-volatile storage device (100), comprising: - at least one array (90) of memory cells with associated decoding and reading circuitry, wherein the array (90) comprises memory cells: - a large number of memory blocks; - at least one dummy line (300) corresponding to a corresponding memory block (160) of the plurality of memory blocks, wherein each dummy line of the at least one dummy line (300): - is assigned to a first address space which is located outside a second address space of the corresponding memory block (160); and - is configured to store internal block variables of a deletion phase and a known pattern; and - a controller (101) which is connected to the array (90) of memory cells, and is configured for each dummy row of at least one dummy row (300): - during each power-up phase of at least one array (90) of memory cells to determine whether a known pattern is stored in the corresponding dummy row, wherein a determination that the known pattern is not stored in the corresponding dummy row indicates an incomplete erasure of the corresponding memory block; and - to delete the corresponding memory block each time it is determined that the known pattern is not stored in the corresponding dummy line.

Inventors

  • Alberto Troia
  • Antonino Mondello

Assignees

  • MICRON TECHNOLOGY, INC.

Dates

Publication Date
20260513
Application Date
20190531

Claims (20)

  1. A non-volatile storage device (100) comprising: - at least one array (90) of memory cells with associated decoding and reading circuitry, wherein the array (90) of memory cells comprises: - a plurality of memory blocks; - at least one dummy row (300) corresponding to a corresponding memory block (160) of the plurality of memory blocks, wherein each dummy row of the at least one dummy row (300): - is assigned to a first address space located outside a second address space of the corresponding memory block (160); and - is configured to store internal block variables of an erase phase and a known pattern; and - a controller (101) which is connected to the array (90) of memory cells and is configured for each dummy row of the at least one dummy row (300): - to determine, during each power-up phase of the at least one array (90) of memory cells, whether a known pattern is stored in the corresponding dummy row, wherein a determination that the known pattern is not stored in the corresponding dummy row indicates an incomplete erasure of the corresponding memory block; and - during each determination that the known pattern is not stored in the corresponding dummy row The goal is to perform a deletion of the corresponding memory block.
  2. Non-volatile storage device (100) according to Claim 1 , wherein the internal block variables include parameters that are usable during the erase phase of the corresponding memory block (160).
  3. Non-volatile storage device (100) according to Claim 1 , wherein the internal block variables include erase pulses and/or target voltages that are applied to the corresponding memory block (160) during the erase phase.
  4. Non-volatile storage device (100) according to one of the Claims 1 until 3 , wherein the plurality of memory blocks is contained in at least one subarray (220) of the array (90) of memory cells.
  5. A system comprising: - a host device; - a non-volatile storage device (100) coupled to the host device and comprising at least one array (90) of memory cells with associated decoding and reading circuitry; - a plurality of memory blocks in the array (90) of memory cells; - at least one dummy row (300) corresponding to a memory block (160) of the plurality of memory blocks, each dummy row of the at least one dummy row (300) being: - assigned to a first address space located outside a second address space of the corresponding memory block (160); and - configured to store internal block variables of an erase phase and a known pattern; and - a controller (101) connected to the array (90) of memory cells, configured for each dummy row of the at least one dummy row (300): - to determine, during each power-up phase of the at least one array (90) of memory cells, whether a known pattern is stored in the corresponding dummy row, wherein a determination that the known pattern is not stored in the corresponding dummy row indicates an incomplete erasure of the corresponding memory block; and- to perform an erasure of the corresponding memory block each time a determination is made that the known pattern is not stored in the corresponding dummy row.
  6. System according to Claim 5 , which is configured to attempt to retrieve previous internal block variables of a previous erase phase from at least one dummy line (300) for the corresponding memory block (160).
  7. System according Claim 6 , which is configured to start the erase phase for the corresponding memory block (160) at least partially based on a successful attempt to retrieve the previous internal block variables.
  8. System according to Claim 6 , wherein the at least one dummy row (300) is provided in another block (160) of the plurality of memory blocks or in a dedicated memory section of the array (90) of memory cells.
  9. System according to Claim 5 , wherein the internal block variables include parameters that are usable during the erase phase of the corresponding memory block (160).
  10. System according to Claim 5 , wherein the internal block variables include erase pulses and target voltages that are applied to the corresponding memory block (160) during the erase phase.
  11. System according Claim 5 , wherein the plurality of memory blocks is contained in at least one subarray (220) of the array (90) of memory cells.
  12. Method for testing an erasure process of a non-volatile storage device (100) comprising at least one array (90) of memory cells with associated decoding and reading circuitry and a controller (101), the method comprising: - performing (810) an erasure phase on a memory block (160) in the at least one array (90) of memory cells of the non-volatile storage device (100); - storing (820, 830) internal block variables of the erasure phase and a known pattern in a dummy line (300) of the memory block (160) before switching on the at least one array (90) of memory cells, wherein the dummy line (300) is assigned to a first address space which is located outside a second address space of the corresponding memory block (160); - Determining whether the known pattern is stored in the corresponding dummy row (300) after activating the at least one array (90) of memory cells, wherein a determination that the known pattern is not stored in the corresponding dummy row indicates an incomplete erasure of the corresponding memory block; and - Performing an erasure operation of the corresponding memory block when it has been determined that the known pattern is not stored in the corresponding dummy line (300).
  13. Procedure according to Claim 12 , wherein the execution of the deletion phase includes the execution of a dynamic deletion operation on the memory block (160).
  14. Procedure according to Claim 12 , wherein the procedure includes invalidating the content of the dummy line (300) before performing the deletion operation.
  15. Procedure according to Claim 12 , where storing the internal block variables includes storing parameters to be used during the erasure phase of the memory block (160).
  16. Procedure according to Claim 12 , wherein storing the internal block variables includes storing erase pulses and target voltages applied to the memory block (160) during the erase phase.
  17. Procedure according to Claim 12 , where the start of the erase phase on memory block (160) is partly based on an unsuccessful attempt to retrieve the previous internal block variables.
  18. Procedure according to Claim 12 , wherein the start of the erase phase includes the restoration of the memory block (160) at least partially based on an unsuccessful attempt to retrieve the previous internal block variables.
  19. A method for erasing a non-volatile memory device (100) comprising at least one array (90) of memory cells with associated decoding and reading circuitry and a controller, wherein the method comprises: - Performing a dynamic erase operation on a memory block (160) in the at least one array (90) of memory cells of the non-volatile memory device (100); - Storing internal block variables of the dynamic erase operation in a dummy row (300) of the memory block (160) before activating the at least one array (90) of memory cells, wherein the dummy row (300) is assigned to a first address space located outside a second address space of the corresponding memory block (160); - Storing a known pattern in the dummy row (300) before activating the at least one array (90) of memory cells; - Determine whether the known pattern is stored in the corresponding dummy row (300) after activating the at least one array (90) of memory cells, whereby a determination that the known pattern is not stored in the corresponding dummy row (300) indicates an incomplete erasure of the corresponding memory block (160); and - Perform an erasure of the corresponding memory block (160) if it has been determined that the known pattern is not stored in the corresponding dummy row (300).
  20. Procedure according to Claim 19 , furthermore, including invalidating the content of the dummy line (300) before performing a dynamic deletion operation.

Description

TECHNICAL AREA The present disclosure relates generally to storage devices and in particular to methods for setting operating parameters of an integrated storage circuit. In particular, the present disclosure relates to a method for self-trimming the operating parameters of a storage device and for checking the erasure phase of the storage device. STATE OF THE ART Storage devices are well-known in the field of electronics for storing and accessing digital information. Generally, various types of semiconductor storage devices can be incorporated into more complex systems that include either non-volatile or volatile memory components, such as in so-called system-on-chips (SoCs), where the aforementioned memory components are embedded. However, nowadays the need for real-time operating systems for automotive applications requires SoCs with ever greater performance and efficiency, and the known solutions no longer meet these requirements. Non-volatile memory can provide persistent data by retaining stored data when it is not powered on, and can include, among other types, NAND flash memory or NOR flash memory. NAND flash has shorter erase and write times and requires less chip area per cell, enabling higher storage density and lower cost per bit than NOR flash. A key feature of flash memory is its ability to erase blocks of data rather than byte at a time. However, a significant drawback of flash memory is its limited capacity for a relatively small number of write and erase cycles within a given block. Flash storage devices can comprise large arrays of memory cells for storing data, often organized in rows and columns. Individual memory cells and/or ranges of memory cells can be addressed by their row and column. When addressing a memory array, there may be one or more layers of address translation to translate, for example, between a logical address used by a host device (i.e., the SoC) and a physical address corresponding to a position in the memory array. US 2016 / 0 322 108 A1 Disclosing a non-volatile memory system with NAND architecture, in which one or more word lines at the ends of a memory block are designated as dummy word lines that are not used for storing user data. These dummy word lines serve to store metadata about the block's state, trim parameters, error statistics, and other status information. Based on this metadata, the memory controller can adjust read parameters or perform block reshuffling. US 2016 / 0 342 494 A1 Disclosure reveals a storage system with non-volatile memory in which each memory block can be monitored with regard to its state and behavior. For this purpose, one or more dummy word lines are used within each block, which are not accessible for normal data storage. These dummy word lines are programmed with a known data pattern that can be read and analyzed to detect potential errors and represent the health of the memory block. Based on this analysis, the operating parameters, such as read voltages, can be adjusted to optimize the performance of each memory block. US 2018 / 0 293 029 A1 This reveals a storage system with non-volatile memory and a controller that responds to temperature differences between data writing and reading. The controller can measure the threshold values (Vt) of memory cells under different parameters and determine correction values to adjust the read threshold accordingly. Additionally, data written at unusual write temperatures is marked as requiring a refresh or stored with increased reliability. In this way, read parameters are adjusted based on temperature to enhance data integrity and storage reliability. Although unusual, it is possible that the address information provided to a storage device on a command/address bus may be corrupted by an error, so that an internal operation of the storage device (e.g., a read operation, a write operation, an erase operation, etc.) may be performed at a different physical address than the one used as the target by a host device or a controller of the storage device. Accordingly, a way to verify that a storage operation was performed at the intended address is required, and the present disclosure focuses on methods for verifying the correctness of the deletion phase. BRIEF DESCRIPTION OF THE DRAWINGS 1 shows a schematic view of a system with a storage component associated with a controller that exchanges data, address, and control signals with the storage device;2 is a schematic view of the storage component according to the present disclosure;3 is a schematic view of the storage component according to the present disclosure;4 is a schematic view of a memory block formed by a plurality of rows of a memory array according to an embodiment of the present disclosure;5 is a schematic view of a group of address registers for a memory page in the memory section of the present disclosure;6 shows in a schematic diagram the distribution of a good deleted/programmed cell (1 bit/cell);7 A diagram shows accordingly 6 , w