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DE-112021002277-B4 - Semiconductor component, manufacturing process and structural wafer object

DE112021002277B4DE 112021002277 B4DE112021002277 B4DE 112021002277B4DE-112021002277-B4

Abstract

Semiconductor component manufacturing process, including: a step which provides a wafer source (1) having a first principal surface (2) on one side and a second principal surface (3) on the other side, and a first support element (11) and a second support element (21); a support step with a first support step in which the wafer source (1) is supported on the side of the first main surface (2) by the first support element (11), and with a second support step in which the wafer source (1) is supported on the side of the second main surface (3) by the second support element (21), wherein the second support step includes bonding a first plate surface (22) of the second support element (21) to the second main surface (3) of the wafer source (1) by a direct bonding process, and wherein a second amorphous bond layer (32) is formed between the second main surface (3) and the first plate surface (22) after bonding, the procedure further features: a step of forming a modified layer (33) in which a modified layer (33) is formed along a horizontal direction parallel to the first principal surface (2) in a thickness-direction intermediate section of the wafer source (1); and a wafer separation step in which a wafer structure (35) containing the second support element (21) and a wafer (34) is separated from the wafer source (1) by means of the modified layer (33), wherein the wafer structure (35) with the second support element (21) and the wafer (34) includes the second amorphous bond layer (32) which bonds the second support element (21) and the wafer (34), and wherein the second amorphous bond layer (32) is formed as a starting point for separating the second support element (21) and the wafer (34) in a subsequent step.

Inventors

  • Minoru Nakagawa

Assignees

  • ROHM CO., LTD.

Dates

Publication Date
20260513
Application Date
20210830
Priority Date
20200917

Claims (19)

  1. Semiconductor device fabrication process, comprising: a step that provides a wafer source (1) having a first principal surface (2) on one side and a second principal surface (3) on the other side, and a first support element (11) and a second support element (21); a support step comprising a first support step in which the wafer source (1) is supported on the side of the first main surface (2) by the first support element (11), and a second support step in which the wafer source (1) is supported on the side of the second main surface (3) by the second support element (21), whereby the second support step includes bonding a first plate surface (22) of the second support element (21) to the second main surface (3) of the wafer source (1) by a direct bonding process, and wherein a second amorphous bond layer (32) is formed between the second main surface (3) and the first plate surface (22) after bonding, whereby the process further comprises: a step of forming a modified layer (33) in which a modified layer (33) is formed along a horizontal direction parallel to the first main surface (2) in a thickness-direction intermediate section of the wafer source (1); and a wafer separation step in which a wafer structure (35) comprising the second support element (21) and a wafer (34) is separated from the wafer source (1) by means of the modified layer (33), whereby the wafer structure (35) comprising the second support element (21) and the wafer (34) includes the second amorphous bonding layer (32) which bonds the second support element (21) and the wafer (34), and whereby the second amorphous bonding layer (32) is formed as a starting point for separating the second support element (21) and the wafer (34) in a subsequent step.
  2. Semiconductor component manufacturing process according to Claim 1 , wherein the first support step includes bonding a first plate surface (12) of the first support element (11) to the first main surface (2) of the wafer source (1) by a direct bonding process, wherein a first amorphous bond layer (31) is formed between the first main surface (2) and the first plate surface (12) after bonding.
  3. Semiconductor component manufacturing process according to Claim 1 or 2 , wherein the wafer source (1) separated from an ingot is provided.
  4. Semiconductor component manufacturing process according to any one of the Claims 1 until 3 , furthermore with: a step that transfers the wafer structure (35).
  5. Semiconductor component manufacturing process according to any one of the Claims 1 until 4 , further comprising: a wafer source reuse step (1) in which a series of steps including the carrier step and the wafer separation step are repeated until it is no longer possible to separate the wafer source (1).
  6. Semiconductor component manufacturing process according to any one of the Claims 1 until 5 , wherein the step of cutting the wafer source (1) includes a step in which the wafer source (1), after the modified layer (33) is formed along the horizontal direction in the thickness-direction intermediate section of the wafer source (1) by a laser light irradiation process, is split in the horizontal direction with the modified layer (33) as a starting point.
  7. Semiconductor component manufacturing process according to any one of the Claims 1 until 6 , furthermore with: a step that forms an epitaxial layer (37) in a section plane of the wafer (34).
  8. Semiconductor component manufacturing process according to Claim 7 , furthermore with: a step that polishes the section plane; wherein the epitaxial layer (37) is formed on the polished surface of the wafer (34).
  9. Semiconductor component manufacturing process according to any one of the Claims 1 until 6 , furthermore with: a step which forms a functional component in the section plane of the wafer (34).
  10. Semiconductor component manufacturing process according to Claim 9 , furthermore with: a step that polishes the section plane; wherein the functional component is formed in the polished surface of the wafer (34).
  11. Semiconductor component manufacturing process according to Claim 9 or 10 , furthermore with: a step that removes the second support element (21) from the wafer (34) after the formation of the functional component.
  12. Semiconductor component manufacturing process according to any one of the Claims 1 until 11 , wherein the second support element (21) is made of the same material as the wafer source (1).
  13. Semiconductor component manufacturing process according to Claim 12 , wherein the wafer source (1) is made of a SiC monocrystal, and wherein the second support element (21) is made of a SiC monocrystal or a SiC polycrystal.
  14. Semiconductor device fabrication process, comprising: a step that provides a first semiconductor (34) and a second semiconductor (21); a step in which the second semiconductor (21) is bonded to the first semiconductor (34) by a direct bonding process to form a semiconductor structure having an amorphous bond layer (32) between the first semiconductor (34) and the second semiconductor (21); a step in which an epitaxial layer (37) is formed on an area layer (42) of the first semiconductor (34) that is not bonded to the second semiconductor (21); a step in which a plurality of device regions (44) are formed on the area layer (42) of the first semiconductor (34); a step in which an internal structure of the functional device is formed in each of the plurality of device regions (44); a step in which the semiconductor structure (34) on the side of the surface layer (42) is supported by a third support element (61); a step in which a modified layer (70) is formed in the amorphous bond layer (32) by means of a laser light irradiation process; and a step in which the semiconductor structure (35) is split, with the modified layer (70) as a starting point, and which separates the first semiconductor (34) and the second semiconductor (21).
  15. Semiconductor component manufacturing process according to Claim 14 , further comprising: a step following the splitting step in which a split surface of the first semiconductor (34) is smoothed in a state in which it is supported by the third support element (61) by a grinding process and/or an etching process; and a step in which a second main surface electrode (71) is formed on the split surface of the first semiconductor (34).
  16. Semiconductor component manufacturing process according to Claim 14 or 15 , wherein the amorphous bond layer (22) is formed which has a light absorption coefficient that is greater than a light absorption coefficient of the first semiconductor (34) .
  17. Semiconductor component manufacturing process according to any one of the Claims 14 until 16 , wherein the first semiconductor (34) is composed of a SiC monocrystal, wherein the second semiconductor (21) is composed of a SiC monocrystal or a SiC polycrystal, and wherein the amorphous bond layer (22) is composed of an amorphous SiC bond layer.
  18. Semiconductor component manufacturing process according to Claim 14 , wherein the first semiconductor (34), the second semiconductor (21) and the amorphous bond layer (32) between the first semiconductor (34) and the second semiconductor (21) are produced by the method according to Claim 1 or Claim 2 be manufactured.
  19. Semiconductor component manufacturing process according to Claim 18 , wherein the first semiconductor (34) and the second semiconductor (21) are separated from the wafer source (1).

Description

Technical field The present invention relates to a semiconductor component manufacturing process. State of the art Patent literature 1 discloses a semiconductor component manufacturing process which includes a step of thinning a semiconductor wafer by grinding and a step of cutting out a plurality of semiconductor chips from the thinned semiconductor wafer. Other semiconductor manufacturing processes are known from the documents US 2016/0336233 A1 and US 2018/0118562 A1 . List of citations Patent literature Patent literature 1: Japanese patent application with publication number [number missing in original text]. JP 2010-016188A Overview of the invention Technical problem A preferred embodiment of the present invention provides a semiconductor device manufacturing method that is capable of improving manufacturing efficiency and provides a wafer structure. Solution to the problem The present invention provides a semiconductor device manufacturing method with the features of claim 1, comprising a step in which a wafer source or wafer feed material or a wafer block (“wafer source”) and a support element are provided, a support step in which the wafer source is supported or mounted by means of the support element, and a wafer separation step in which the wafer source is cut (“cut”) in a horizontal direction from or through a thickness-direction intermediate section or a thickness-direction middle section of the wafer source in order to separate (“separate”) a wafer structure from the wafer source, which includes the support element and a wafer that has been cut away from the wafer source. The present invention further provides a semiconductor device manufacturing method with the features of claim 14, comprising a step in which a first semiconductor and a second semiconductor are provided, a step in which the second semiconductor is bonded to the first semiconductor by means of a direct bonding process to form a semiconductor structure having an amorphous bond layer between the first semiconductor and the second semiconductor, a step in which a modified layer is formed in the amorphous bond layer by means of a laser light irradiation process, and a step in which the semiconductor structure is cleaved, with the modified layer as a starting point, and which separates the first semiconductor and the second semiconductor. Furthermore, a wafer structure is disclosed which includes a first wafer, a second wafer which carries or supports the first wafer, and an amorphous bonding layer which is arranged between the first wafer and the second wafer and which bonds the first and the second wafer to each other. The above-mentioned as well as further tasks, features and effects of the present invention will become clearer from the following description of the preferred embodiments with reference to the accompanying drawings. Brief description of the drawings 1 Figure 1 is a perspective view showing a SiC wafer source, a first support element and a second support element used in a SiC semiconductor component manufacturing process according to a first preferred embodiment of the present invention.2 is a flowchart that shows an example of the SiC semiconductor device manufacturing process implemented with respect to the SiC wafer source.3A This is a cross-sectional view to describe an example of the SiC semiconductor device fabrication process implemented with respect to the SiC wafer source.3B is a cross-sectional view used to describe a step similar to that of 3A follows.3C is a cross-sectional view used to describe a step similar to that of 3B follows.3D is a cross-sectional view used to describe a step similar to that of 3C follows.3E is a cross-sectional view used to describe a step similar to that of 3D follows.3F is a cross-sectional view used to describe a step similar to that of 3E follows.3G This is a cross-sectional view to describe a step that follows that of IG. 3F.3H is a cross-sectional view used to describe a step similar to that of 3G follows.3I is a cross-sectional view used to describe a step similar to that of 3H follows.4 is a flowchart that shows an example of the SiC semiconductor device manufacturing process implemented in relation to a wafer structure.5A This is a cross-sectional view showing an example of the SiC semiconductor device manufacturing process implemented in relation to the wafer structure.5B is a cross-sectional view used to describe a step similar to that of 5A follows.5C is a cross-sectional view used to describe a step similar to that of 5B follows.5D is a cross-sectional view used to describe a step similar to that of 5C follows.5E is a cross-sectional view used to describe a step similar to that of 5D follows.5F is a cross-sectional view used to describe a step similar to that of 5E follows.5G is a cross-sectional view used to describe a step similar to that of 5F follows.5H is a cross-sectional view used to describe a step similar to that of 5G follows.5I is a cross-sectional view u