DE-112023006491-T5 - INTEGRATED CIRCUIT DEVICE WITH MULTI-LENGTH GATE ELECTRODE

Abstract

An integrated circuit (IC) device features a gate electrode of multiple lengths. The length of a first gate electrode segment, located over a channel region in one semiconductor structure, can be longer (e.g., approximately 0.5–3 nm longer) than the length of a second gate electrode segment, located over a channel region in another semiconductor structure. The grid dimensions of the two gate electrode segments can be the same or substantially similar. The gate electrode lengths can be differentiated by using dry-cleaning-based removal of a dielectric material surrounding the semiconductor structures. In a first segment, a greater amount of dielectric material can be removed than in a second segment, so the gap in the first segment can be longer than the gap in the second. A conductive material can be provided to fill the gaps to form the gate electrode.

Inventors

• Hwichan Jun
• Edward Yeh
• Robin Chao

Assignees

• INTEL CORPORATION

Dates

Publication Date

20260513

Application Date

20231206

Priority Date

20230613

Claims (20)

1. Integrated circuit (IC) device comprising: a first conductive structure with a first longitudinal axis; a second conductive structure with a second longitudinal axis that is substantially parallel to the first longitudinal axis; a first semiconductor structure; and a second semiconductor structure above the first semiconductor structure, where: a first section of the first conductive structure is located above a section of the first semiconductor structure, a second section of the first conductive structure is located above a section of the second semiconductor structure, a dimension of the first section in a direction that is substantially perpendicular to the first longitudinal axis is greater than a dimension of the second section in that direction, and a distance from a center of the first section to the second longitudinal axis is equal to or substantially similar to a distance from a center of the second section to the second longitudinal axis.
2. IC device according to Claim 1 , where the difference between the dimension of the first section and the dimension of the second section is up to approximately 3 nanometers.
3. IC device according to Claim 2 , wherein the difference between the dimension of the first section and the dimension of the second section is at least approximately 0.5 nanometers.
4. IC device according to one of the Claims 1 - 3 , which further comprises: a first dielectric structure over the first section of the first conductive structure in the direction; and a second dielectric structure over the second section of the first conductive structure in the direction.
5. IC device according to Claim 4 , where one dimension of the first dielectric structure in the direction is smaller than one dimension of the second dielectric structure in the direction.
6. IC device according to one of the Claims 1 - 3 , further comprising: a first dielectric structure at least partially between the first section of the first conductive structure and the section of the first semiconductor structure; and a second dielectric structure at least partially between the second section of the first conductive structure and the section of the second semiconductor structure.
7. IC device according to Claim 6 , where one dimension of the first dielectric structure in the direction is smaller than one dimension of the second dielectric structure in the direction.
8. IC device according to one of the Claims 1 - 3 , which further comprises: a first dielectric region over the first section of the first conductive structure in a different direction, which is substantially perpendicular to the direction and the first longitudinal axis; and a second dielectric region over the second section of the first conductive structure in the different direction.
9. IC device according to Claim 8 , where one dimension of the first dielectric region is smaller than one dimension of the second dielectric region.
10. IC device according to one of the Claims 1 - 9 , where the first semiconductor structure has a fin or a nanoribbon.
11. Integrated circuit (IC) device comprising: a first transistor comprising a first source region, a first drain region, and a first channel region, wherein the first source region is located above the first drain region along a horizontal axis of the IC device; a second transistor above the first transistor along a vertical axis of the IC device, wherein the second transistor comprises a second source region, a second drain region, and a second channel region; a first gate electrode comprising a first section and a second section, wherein the first section is located above the first channel region and the second section is located above the second channel region; and a second gate electrode above the first gate electrode along a horizontal axis of the IC device, where a dimension of the first section along the horizontal axis is greater than a dimension of the second section along the horizontal axis, and a distance from the first section to the second gate electrode along the horizontal axis is equal to or substantially similar to a distance from the second section to the second gate electrode.
12. IC device according to Claim 11 , where the following applies: the first gate electrode has a longitudinal axis along the vertical axis, and the first source region, a first drain region and a first channel region are located in a semiconductor structure with a longitudinal axis along the horizontal axis.
13. IC device according to Claim 12 , wherein the semiconductor structure comprises a fin or a nanoribbon.
14. IC device according to one of the Claims 11 - 13 , wherein the following applies: the first source region, a first drain region and a first channel region are located in a first semiconductor structure, the second source region, a second drain region and a second channel region are located in a second semiconductor structure, and the first semiconductor structure is located above the second semiconductor structure in a direction along the vertical axis.
15. IC device according to one of the Claims 11 - 14 , where the following holds: the second gate includes a third section and a fourth section, and a dimension of the third section along the horizontal axis is larger than a dimension of the fourth section along the horizontal axis.
16. IC device according to one of the Claims 11 - 15 , where the difference between the dimension of the first section and the dimension of the second section is in a range of approximately 0.5 nanometers to approximately 3 nanometers.
17. IC device according to one of the Claims 11 - 16 , wherein the following applies: the first transistor further comprises a first gate insulator between the first section of the first gate electrode and the first channel region; and the second transistor further comprises a second gate insulator between the second section of the first gate electrode and the second channel region.
18. IC device according to Claim 17 , where one dimension of the first gate insulator along the horizontal axis is smaller than one dimension of the second gate insulator along the horizontal axis.
19. A method for forming an integrated circuit (IC) device, comprising: forming a semiconductor structure over a substrate; forming a dielectric structure, wherein the semiconductor structure is at least partially surrounded by the dielectric structure; reducing a dimension of a first section of the dielectric structure to a first predetermined dimension; reducing a dimension of a second section of the dielectric structure to a second predetermined dimension; and forming a conductive structure, in which a first section of the conductive structure is located between a first section of the semiconductor structure and the first section of the dielectric structure, and a second section of the conductive structure is located between a second section of the semiconductor structure and the second section of the dielectric structure.
20. Procedure according to Claim 19 , wherein reducing the dimension of the second section of the dielectric structure to the second predetermined dimension comprises: reducing the dimension of the second section of the dielectric structure to the first predetermined dimension.

Description

Cross-reference to related registration This application claims priority from US patent application no. 18/333,758 , submitted on June 13, 2023 and entitled “INTEGRATED CIRCUIT DEVICE WITH MULTI-LENGTH GATE ELECTRODE”, which is hereby incorporated herein by reference in its entirety. background The fabrication of integrated circuits (ICs) typically involves two stages. The first stage is called the front-end-of-line (FEOL). The second stage is called the back-end-of-line (BEOL). In the FEOL, individual semiconductor device components (e.g., transistors, capacitors, resistors, etc.) are structured onto a wafer. In the BEOL, metal layers, vias, and insulating layers are formed to connect the individual components. The BEOL usually begins with the formation of the first metal layer on the wafer. This first metal layer is often designated M0. Additional metal layers can be formed on top of M0, and these metal layers are often designated M1, M2, and so on. Standard cell methodology is a popular technique for designing integrated circuit devices, such as application-specific ICs. A standard cell can provide a logic function (e.g., AND, OR, XOR, etc.), a storage function (e.g., flip-flop, latch, etc.), other types of functions, or a combination thereof. A standard cell typically includes a group of transistors and interconnect structures, such as a group of parallel gate electrodes stacked along a horizontal axis of the standard cell. The width of a standard cell can depend on the number of gate electrodes along its horizontal axis. The distance between two immediately adjacent gate electrodes along the standard cell's horizontal axis can be referred to as the contacted poly grid (CPP) dimension. Brief description of the drawings The embodiments are readily understood from the following detailed description in conjunction with the accompanying drawings. To simplify this description, identical reference numerals denote identical structural elements. The embodiments are illustrated in the figures of the accompanying drawings as examples and are not exhaustive. 1 is a perspective view of an IC device with a gate electrode of multiple lengths according to some embodiments of the disclosure. 2 Illustrates an IC device with a FEOL section having a gate electrode of multiple lengths and a BEOL section according to some embodiments of the disclosure. The 3A and 3B are cross-sectional views of an IC device with a gate electrode of multiple lengths according to some embodiments of the disclosure. 4 is a top view of an IC device with a gate electrode of multiple lengths according to some embodiments of the disclosure. The 5A-5L illustrate a manufacturing process of an IC device with a gate electrode of multiple lengths according to some embodiments of the disclosure. The 6A-6B are top views of a wafer and of matrices that can enable one or more IC devices with gate electrodes of multiple lengths, according to some embodiments of the disclosure. 7 Figure 1 is a lateral cross-sectional view of an exemplary IC package which may include one or more IC devices with gate electrodes of multiple lengths, according to some embodiments of the disclosure. 8 is a lateral cross-sectional view of an IC device assembly which may include components with one or more IC devices having gate electrodes of multiple lengths, according to some embodiments of the disclosure. 9 is a block diagram of an exemplary computing device which may have one or more components with one or more IC devices having gate electrodes of multiple lengths, according to some embodiments of the disclosure. Detailed description The systems, methods, and devices of this disclosure each have several novel aspects, none of which alone accounts for all the desirable attributes disclosed herein. Details of one or more implementations of the subject matter described in this specification are set forth in the description below and in the accompanying drawings. The dimension of a gate electrode in one direction along the horizontal axis of a standard cell is usually referred to as the gate electrode length or gate length, Lg. The gate length can be the distance between the source region and a drain region of a transistor. Gate length modulation in the same CPP is typically achieved by modifying the thickness of the self-aligned double-structured (SADP) spacer (also called a "gate spacer"). However, spacer modulation can introduce more complexity into the SADP process. Spacer modulation also has the limitation of a minimum thickness gap. It can also cause source-drain opening width variations, which can lead to variations in epitaxial growth. One solution is to use an additional deposition of a thin spacer to increase the gate length. Adding a thin spacer can limit the minimum Lg increment due to the lower thickness limit of the thin spacer deposition process. Another solution is to use a trimming process (e.g., etching) to thin an SADP spacer and reduce the gate length. However,