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DE-112023006736-T5 - Semiconductor Device and Method for Manufacturing a Semiconductor Device

DE112023006736T5DE 112023006736 T5DE112023006736 T5DE 112023006736T5DE-112023006736-T5

Abstract

Semiconductor device (100) comprising a semiconductor body (1) with at least one contact region (11) of a first conductivity type, at least one base region (12) of a second conductivity type, a drift region (14) of the first conductivity type and a deep well (16) of the second conductivity type, wherein the base region (12) has a principal extent in a first lateral direction (L1), the at least one contact region (11) is embedded in the at least one base region (12) such that the at least one contact region (11) is separated from the drift region (14) by the at least one base region (12), wherein the deep well (16) is embedded in the drift region (14) such that the deep well (16) is separated from the at least one base region (12) by the drift region (14). The semiconductor (100) comprises a field oxide region (17) with a second thickness (T2) having a principal extent direction in a second lateral direction (L2), wherein the field oxide region (17) is located on the drift region (14) and at least partially covers the deep well (16) in the second lateral direction (L2). The semiconductor device (100) comprises a gate electrode (3) comprising at least two parts (30) spaced apart from each other in the second lateral direction (L2), wherein the at least two parts (30) overlap with parts of the base region (12) in the second lateral direction (L2) and wherein the at least two parts (30) overlap with parts of the field oxide region (17) in an overlap region (8) in the second lateral direction (L2), and a first main electrode (2) electrically contacts the at least one contact region (11).

Inventors

  • Gaurav Gupta
  • Luca DE MICHIELIS

Assignees

  • HITACHI ENERGY LTD

Dates

Publication Date
20260513
Application Date
20230824
Priority Date
20230731

Claims (15)

  1. Semiconductor device (100), comprising: - a semiconductor body (1) with at least one contact region (11) of a first conductivity type, at least one base region (12) of a second conductivity type, a drift region (14) of the first conductivity type, and a deep well (16) of the second conductivity type, wherein: - the base region (12) has a principal extent in a first lateral direction (L1), - the at least one contact region (11) is embedded in the at least one base region (12) such that the at least one contact region (11) is separated from the drift region (14) by the at least one base region (12), and wherein: - the deep well (16) is embedded in the drift region (14) such that the deep well (16) is separated from the at least one base region (12) by the drift region (14), - a field oxide region (17) with a second thickness (T2), which the main extension direction in a second lateral direction (L2), wherein: - the field oxide region (17) is located on the drift region (14) and at least partially covers the deep trough (16) in the second lateral direction (L2); - a gate electrode (3) comprising at least two parts (30) spaced apart from each other in the second lateral direction (L2), wherein: - the at least two parts (30) overlap with parts of the base region (12) in the second lateral direction (L2); and wherein: - the at least two parts (30) overlap with parts of the field oxide region (17) in an overlap region (8) in the second lateral direction (L2); and - a first main electrode (2) electrically contacts the at least one contact region (11).
  2. Semiconductor device (100) according to Claim 1 , wherein - the gate electrode (3) is electrically isolated from the semiconductor body (2) and - the semiconductor device (100) is configured such that during operation the at least two parts (30) of the gate electrode (3) deplete the areas of the base region (12) with which they overlap.
  3. Semiconductor device (100) according to Claim 1 or 2 , wherein the at least two parts (30) of the gate electrode (3) are at least partially located on a gate oxide (32) with a first thickness (T1), wherein - the gate oxide (32) is at least partially located on the semiconductor body (1), and wherein - the gate oxide (32) electrically insulates the gate electrode (3) from the semiconductor body (1).
  4. Semiconductor device (100) according to Claim 3 , wherein the second thickness (T2) of the field oxide region (17) is greater than or equal to the first thickness (T1) of the gate oxide (32).
  5. Semiconductor device (100) according to one of the preceding claims, wherein the gate electrode (3) comprises a third part (31) which is arranged along the second lateral direction (L2) between the first two parts (30).
  6. Semiconductor device (100) according to Claim 5 , wherein the first main electrode (2) electrically contacts the third part (31).
  7. Semiconductor device (100) according to Claim 5 , wherein the third part (31) is electrically insulated from the first main electrode (2).
  8. Semiconductor device (100) according to one of the preceding claims, wherein - the base region (12) has a first depth (D1) in the vertical direction (V), and - the deep well (16) has a second depth (D2) in a vertical direction (V), wherein - the second depth (D2) is greater than the first depth (D1).
  9. Semiconductor device (100) according to one of the preceding claims, wherein the deep well (16) is positioned at a first lateral distance (P1) from the base region (12), wherein the first lateral distance (P1) is the shortest possible lateral distance between the base region (12) and the deep well (16).
  10. Semiconductor device (100) according to one of the preceding claims, wherein the deep well (16) is connected to the first main electrode (2) in the second lateral direction (L2).
  11. Semiconductor device (100) according to one of the preceding claims, wherein the overlap area (8) of the at least two parts (30) and the field oxide region (17) is in the range of 1 µm to 10 µm, in particular in the range of 2 µm to 5 µm.
  12. Method for fabricating a semiconductor device (100) comprising the following steps: - providing a base semiconductor body (1') with a drift region (14) of a first conductivity type, - forming a deep well (16) of a second conductivity type in the drift region (14) by implantation, - forming a field oxide region (17) of a second thickness (T2) on the drift region (14) by thermal oxidation, - structuring the field oxide region (17) by removing part of the field oxide region (17) using an active mask, - growing a gate oxide (32) with a first thickness (T1) on the drift region (14), - depositing a gate electrode (3) onto the gate oxide (32) and the field oxide (17), - structuring the gate electrode (3) using a split-gate mask (6) such that - the gate electrode (3) is formed with at least two parts (30) spaced apart in a second lateral direction (L2), - producing a semiconductor body (1) from the base semiconductor body (1') by forming at least one contact region (11) of the first conductivity type and a base region (12) of a second conductivity, wherein - the at least one contact region (11) is embedded in the at least one base region (12) such that the at least one contact region (11) is separated from the drift region (14) by the at least one base region (12), wherein - the at least two parts (30) of the gate electrode (31) overlap with parts of the base region (12), and - removal of the remaining gate oxide (32).
  13. Procedure according to Claim 12 , comprising: - depositing and structuring an interlayer dielectric (19) after the remaining gate oxide (32) has been removed, - forming a first main electrode (2) which electrically contacts the at least one contact area (11), and - forming a second main electrode (4).
  14. Procedure according to Claim 12 or 13 , wherein the formation of the gate electrode (3) with the split-gate mask (6) includes the formation of a third part (31) which is positioned along the second lateral direction (L2) between the first two parts (30).
  15. Procedure according to Claim 12 , 13 or 14 , wherein the formation of a third part (31) comprises electrically contacting the first main electrode (2) with the third part (31).

Description

The present disclosure relates to a semiconductor device and a method for manufacturing a semiconductor device. One objective is to provide a semiconductor device that contributes to improved switching characteristics, particularly without impairing static properties such as conduction losses. Another objective is to provide a method for manufacturing such a semiconductor device. First, the semiconductor device is specified. According to one embodiment, the semiconductor device comprises a semiconductor body with at least one contact region of a first conductivity type, at least one base region of a second conductivity type, a drift region of the first conductivity type, and a deep well of the second conductivity type. The base region has a principal extent in a first lateral direction. The at least one contact region is embedded in the at least one base region such that the base region separates the contact region from the drift region. The deep well is embedded in the drift region such that the drift region separates the deep well from the base region. The semiconductor device further comprises a field oxide region with a second thickness, exhibiting a principal extent direction in a second lateral direction. The field oxide region is located on the drift region and at least partially covers the deep trough in the second lateral direction. The semiconductor device further comprises a gate electrode comprising at least two parts spaced apart in the second lateral direction. The at least two parts of the gate electrode overlap in the second lateral direction with portions of the base region, and the at least two parts of the gate electrode overlap in the second lateral direction with portions of the field oxide in an overlap region. The semiconductor device further comprises a first main electrode that electrically contacts the at least one contact region. The present invention is based, among other things, on the concept of providing a gate electrode that has spaced-apart parts in the second lateral direction, i.e., a split-gate concept is implemented. This reduces parasitic capacitances (e.g., reduced gate-collector and gate-source overlap) and thus improves the switching characteristics. In particular, gate charge and switching losses are reduced at the same collector-emitter saturation voltage (Vce-sat). Furthermore, lower gate leakage is achieved due to the reduced gate area coverage. Additionally, a deep well is arranged in the region between the at least two parts of the gate electrode to prevent any adverse effect of a split-gate design on the device's blocking characteristics. This deep well is of the second conductivity type and extends into the semiconductor body. Furthermore, such a deep well, in combination with the split-gate design, prevents premature breakdown at the edge of the gate electrode facing the deep well. The deep well can be electrically contacted by the first main electrode. The deep well is formed, for example, by implanting boron in the drift region. Any chemical element from group 13 can be used as the material for implantation. The semiconductor body comprises, for example, silicon or silicon carbide (SiC). The semiconductor body may have a principal plane of extension. Lateral directions are directions parallel to the principal plane of extension. The semiconductor body has a top and a bottom face relative to the top face. The top and bottom faces may be at least partially parallel to the principal plane of extension. The contact region can be adjacent to the top surface of the semiconductor body. In other words, the contact region can form part of the top surface of the semiconductor body. The first contact region is of a first conductivity type, which can be n-type, i.e., it can be n-doped. The contact region is also referred to as the "source region." For example, the maximum and/or average doping concentration in the contact region is at least 10 <sup>18</sup> cm<sup> -3 </sup>, 10<sup> 19 </sup> cm <sup>-3</sup> , or 10<sup>20</sup> cm <sup>-3 </sup>. The base region can be adjacent to the contact region. In particular, the base region partially surrounds the contact region. The base region can separate the contact region from the drift region, so that there is no direct contact between the contact region and the drift region. For example, the contact region may be adjacent only to the base region and to no other region of the semiconductor body. The base region is also referred to as the "well region" or "channel region." The base region can be adjacent to the top surface, i.e., form part of the top surface of the semiconductor body. The basal region has a second conductivity type that is opposite to the first. This second conductivity type can be the p-type, meaning the basal region can be p-doped. The maximum and/or mean doping concentration in the basal region is, for example, at least 10, 100, or 1000 times lower than the minimum and/or mean doping concentration in